diff options
Diffstat (limited to 'tests/arch/anlogic')
| -rw-r--r-- | tests/arch/anlogic/counter.ys | 2 | ||||
| -rw-r--r-- | tests/arch/anlogic/lutram.ys (renamed from tests/arch/anlogic/memory.ys) | 6 |
2 files changed, 4 insertions, 4 deletions
diff --git a/tests/arch/anlogic/counter.ys b/tests/arch/anlogic/counter.ys index d363ec24e..a6eab248c 100644 --- a/tests/arch/anlogic/counter.ys +++ b/tests/arch/anlogic/counter.ys @@ -2,7 +2,7 @@ read_verilog ../common/counter.v hierarchy -top top proc flatten -equiv_opt -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +equiv_opt -assert -multiclock -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/arch/anlogic/memory.ys b/tests/arch/anlogic/lutram.ys index 87b93c2fe..9ebb75443 100644 --- a/tests/arch/anlogic/memory.ys +++ b/tests/arch/anlogic/lutram.ys @@ -1,5 +1,5 @@ -read_verilog ../common/memory.v -hierarchy -top top +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r proc memory -nomap equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic @@ -11,7 +11,7 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter #sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter design -load postopt -cd top +cd lutram_1w1r select -assert-count 8 t:AL_MAP_LUT2 select -assert-count 8 t:AL_MAP_LUT4 |