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-rw-r--r--tests/arch/gatemate/logic.ys6
1 files changed, 3 insertions, 3 deletions
diff --git a/tests/arch/gatemate/logic.ys b/tests/arch/gatemate/logic.ys
index 2718375a2..026406bc8 100644
--- a/tests/arch/gatemate/logic.ys
+++ b/tests/arch/gatemate/logic.ys
@@ -4,7 +4,7 @@ proc
equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
-select -assert-count 1 t:CC_LUT1
-select -assert-count 6 t:CC_LUT2
-select -assert-count 2 t:CC_LUT4
+select -assert-max 1 t:CC_LUT1
+select -assert-max 6 t:CC_LUT2
+select -assert-max 2 t:CC_LUT4
select -assert-none t:CC_LUT1 t:CC_LUT2 t:CC_LUT4 %% t:* %D