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Diffstat (limited to 'tests/arch/quicklogic/add_sub.ys')
| -rw-r--r-- | tests/arch/quicklogic/add_sub.ys | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/tests/arch/quicklogic/add_sub.ys b/tests/arch/quicklogic/add_sub.ys index 168b3f8b3..73ee5cb44 100644 --- a/tests/arch/quicklogic/add_sub.ys +++ b/tests/arch/quicklogic/add_sub.ys @@ -3,9 +3,9 @@ hierarchy -top top equiv_opt -assert -map +/quicklogic/lut_sim.v -map +/quicklogic/pp3_cells_sim.v synth_quicklogic -family pp3 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 3 t:LUT2 -select -assert-count 4 t:LUT3 -select -assert-count 4 t:LUT4 +select -assert-count 2 t:LUT2 +select -assert-count 8 t:LUT3 +select -assert-count 2 t:LUT4 select -assert-count 8 t:inpad select -assert-count 8 t:outpad select -assert-none t:LUT2 t:LUT3 t:LUT4 t:inpad t:outpad %% t:* %D |