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-rw-r--r--tests/arch/xilinx/attributes_test.ys12
1 files changed, 2 insertions, 10 deletions
diff --git a/tests/arch/xilinx/attributes_test.ys b/tests/arch/xilinx/attributes_test.ys
index 58552d8fb..74861850f 100644
--- a/tests/arch/xilinx/attributes_test.ys
+++ b/tests/arch/xilinx/attributes_test.ys
@@ -11,7 +11,7 @@ read_verilog ../common/memory_attributes/attributes_test.v
hierarchy -top distributed_ram
synth_xilinx -top distributed_ram -noiopad
cd distributed_ram # Constrain all select calls below inside the top module
-select -assert-count 8 t:RAM32X1D
+select -assert-count 1 t:RAM32M
# Set ram_style distributed to blockram memory; will be implemented as distributed
design -reset
@@ -19,7 +19,7 @@ read_verilog ../common/memory_attributes/attributes_test.v
setattr -set ram_style "distributed" block_ram/m:*
synth_xilinx -top block_ram -noiopad
cd block_ram # Constrain all select calls below inside the top module
-select -assert-count 32 t:RAM128X1D
+select -assert-count 16 t:RAM256X1S
# Set synthesis, logic_block to blockram memory; will be implemented as distributed
design -reset
@@ -28,7 +28,6 @@ setattr -set logic_block 1 block_ram/m:*
synth_xilinx -top block_ram -noiopad
cd block_ram # Constrain all select calls below inside the top module
select -assert-count 0 t:RAMB18E1
-select -assert-count 32 t:RAM128X1D
# Set ram_style block to a distributed memory; will be implemented as blockram
design -reset
@@ -36,10 +35,3 @@ read_verilog ../common/memory_attributes/attributes_test.v
synth_xilinx -top distributed_ram_manual -noiopad
cd distributed_ram_manual # Constrain all select calls below inside the top module
select -assert-count 1 t:RAMB18E1
-
-# Set synthesis, ram_block block to a distributed memory; will be implemented as blockram
-design -reset
-read_verilog ../common/memory_attributes/attributes_test.v
-synth_xilinx -top distributed_ram_manual_syn -noiopad
-cd distributed_ram_manual_syn # Constrain all select calls below inside the top module
-select -assert-count 1 t:RAMB18E1