diff options
Diffstat (limited to 'tests/arch/xilinx')
| -rw-r--r-- | tests/arch/xilinx/priority_memory.v | 122 | ||||
| -rw-r--r-- | tests/arch/xilinx/priority_memory.ys | 60 |
2 files changed, 182 insertions, 0 deletions
diff --git a/tests/arch/xilinx/priority_memory.v b/tests/arch/xilinx/priority_memory.v new file mode 100644 index 000000000..fc943e209 --- /dev/null +++ b/tests/arch/xilinx/priority_memory.v @@ -0,0 +1,122 @@ +module priority_memory ( + clk, wren_a, rden_a, addr_a, wdata_a, rdata_a, + wren_b, rden_b, addr_b, wdata_b, rdata_b + ); + + parameter ABITS = 12; + parameter WIDTH = 72; + + input clk; + input wren_a, rden_a, wren_b, rden_b; + input [ABITS-1:0] addr_a, addr_b; + input [WIDTH-1:0] wdata_a, wdata_b; + output reg [WIDTH-1:0] rdata_a, rdata_b; + + `ifdef USE_HUGE + (* ram_style = "huge" *) + `endif + reg [WIDTH-1:0] mem [0:2**ABITS-1]; + + integer i; + initial begin + rdata_a <= 'h0; + rdata_b <= 'h0; + end + + `ifndef FLIP_PORTS + always @(posedge clk) begin + // A port + if (wren_a) + mem[addr_a] <= wdata_a; + else if (rden_a) + rdata_a <= mem[addr_a]; + + // B port + if (wren_b) + mem[addr_b] <= wdata_b; + else if (rden_b) + if (wren_a && addr_a == addr_b) + rdata_b <= wdata_a; + else + rdata_b <= mem[addr_b]; + end + `else // FLIP PORTS + always @(posedge clk) begin + // A port + if (wren_b) + mem[addr_b] <= wdata_b; + else if (rden_b) + rdata_b <= mem[addr_b]; + + // B port + if (wren_a) + mem[addr_a] <= wdata_a; + else if (rden_a) + if (wren_b && addr_a == addr_b) + rdata_a <= wdata_b; + else + rdata_a <= mem[addr_a]; + end + `endif +endmodule + +module sp_write_first (clk, wren_a, rden_a, addr_a, wdata_a, rdata_a); + + parameter ABITS = 12; + parameter WIDTH = 72; + + input clk; + input wren_a, rden_a; + input [ABITS-1:0] addr_a; + input [WIDTH-1:0] wdata_a; + output reg [WIDTH-1:0] rdata_a; + + (* ram_style = "huge" *) + reg [WIDTH-1:0] mem [0:2**ABITS-1]; + + integer i; + initial begin + rdata_a <= 'h0; + end + + + always @(posedge clk) begin + // A port + if (wren_a) + mem[addr_a] <= wdata_a; + if (rden_a) + if (wren_a) + rdata_a <= wdata_a; + else + rdata_a <= mem[addr_a]; + end +endmodule + +module sp_read_first (clk, wren_a, rden_a, addr_a, wdata_a, rdata_a); + + parameter ABITS = 12; + parameter WIDTH = 72; + + input clk; + input wren_a, rden_a; + input [ABITS-1:0] addr_a; + input [WIDTH-1:0] wdata_a; + output reg [WIDTH-1:0] rdata_a; + + (* ram_style = "huge" *) + reg [WIDTH-1:0] mem [0:2**ABITS-1]; + + integer i; + initial begin + rdata_a <= 'h0; + end + + + always @(posedge clk) begin + // A port + if (wren_a) + mem[addr_a] <= wdata_a; + if (rden_a) + rdata_a <= mem[addr_a]; + end +endmodule diff --git a/tests/arch/xilinx/priority_memory.ys b/tests/arch/xilinx/priority_memory.ys new file mode 100644 index 000000000..d0b2a16ad --- /dev/null +++ b/tests/arch/xilinx/priority_memory.ys @@ -0,0 +1,60 @@ + +# no uram by default +design -reset +read_verilog priority_memory.v +synth_xilinx -family xcup -top priority_memory +select -assert-none t:URAM288 + +# uram parameter +design -reset +read -define USE_HUGE +read_verilog priority_memory.v +synth_xilinx -family xcup -top priority_memory -noiopad +select -assert-count 1 t:URAM288 + +# uram option +design -reset +read_verilog priority_memory.v +synth_xilinx -family xcup -top priority_memory -noiopad -uram +# check for URAM block +select -assert-count 1 t:URAM288 +# check port A in code maps to port A in hardware: +# %co:+[DOUT_A] selects everything connected to a URAM288.DOUT_A port +# w:rdata_a selects the wire rdata_a +# %i finds the intersection of the two above selections +# if the result is 1 then the wire rdata_a is connected to Port A correctly +select -assert-count 1 t:URAM288 %co:+[DOUT_A] w:rdata_a %i +# we expect no more than 2 LUT2s to control the hardware priority +# if there are extra LUTs, then it is likely emulating logic it shouldn't +# ignore anything using blif, since that doesn't seem to support priority logic +# and is indicative of using verific/tabby +select -assert-max 2 t:LUT* n:*blif* %d + +# reverse priority +design -reset +read -define FLIP_PORTS +read_verilog priority_memory.v +synth_xilinx -family xcup -top priority_memory -noiopad -uram +# test priority is mapped correctly, rdata_a should now be connected to Port B +# see above for details +select -assert-count 1 t:URAM288 %co:+[DOUT_B] w:rdata_a %i + +# sp write first +design -reset +read_verilog priority_memory.v +synth_xilinx -family xcup -top sp_write_first -noiopad +select -assert-count 1 t:URAM288 +# write first connects rdata_a to port B +# similar to above, but also tests that rdata_a *isn't* connected to port A +select -assert-none 1 t:URAM288 %co:+[DOUT_A] w:rdata_a %i +select -assert-count 1 t:URAM288 %co:+[DOUT_B] w:rdata_a %i + +# sp read first +design -reset +read_verilog priority_memory.v +synth_xilinx -family xcup -top sp_read_first -noiopad +select -assert-count 1 t:URAM288 +# read first connects rdata_a to port A +# see above for details +select -assert-count 1 t:URAM288 %co:+[DOUT_A] w:rdata_a %i +select -assert-none 1 t:URAM288 %co:+[DOUT_B] w:rdata_a %i |