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-rw-r--r--tests/arch/xilinx/asym_ram_sdp.ys50
-rw-r--r--tests/arch/xilinx/asym_ram_sdp_read_wider.v72
-rw-r--r--tests/arch/xilinx/asym_ram_sdp_write_wider.v71
-rw-r--r--tests/arch/xilinx/priority_memory.v122
-rw-r--r--tests/arch/xilinx/priority_memory.ys60
5 files changed, 375 insertions, 0 deletions
diff --git a/tests/arch/xilinx/asym_ram_sdp.ys b/tests/arch/xilinx/asym_ram_sdp.ys
new file mode 100644
index 000000000..37f6f314d
--- /dev/null
+++ b/tests/arch/xilinx/asym_ram_sdp.ys
@@ -0,0 +1,50 @@
+# Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1
+
+# w4b | r16b
+design -reset
+read_verilog asym_ram_sdp_read_wider.v
+synth_xilinx -top asym_ram_sdp_read_wider -noiopad
+select -assert-count 1 t:RAMB18E1
+
+# w8b | r16b
+design -reset
+read_verilog asym_ram_sdp_read_wider.v
+chparam -set WIDTHA 8 -set SIZEA 512 -set ADDRWIDTHA 9 asym_ram_sdp_read_wider
+synth_xilinx -top asym_ram_sdp_read_wider -noiopad
+select -assert-count 1 t:RAMB18E1
+
+# w4b | r32b
+design -reset
+read_verilog asym_ram_sdp_read_wider.v
+chparam -set WIDTHB 32 -set SIZEB 128 -set ADDRWIDTHB 7 asym_ram_sdp_read_wider
+synth_xilinx -top asym_ram_sdp_read_wider -noiopad
+select -assert-count 1 t:RAMB18E1
+
+# w16b | r4b
+design -reset
+read_verilog asym_ram_sdp_write_wider.v
+synth_xilinx -top asym_ram_sdp_write_wider -noiopad
+select -assert-count 1 t:RAMB18E1
+
+# w16b | r8b
+design -reset
+read_verilog asym_ram_sdp_write_wider.v
+chparam -set WIDTHB 8 -set SIZEB 512 -set ADDRWIDTHB 9 asym_ram_sdp_read_wider
+synth_xilinx -top asym_ram_sdp_write_wider -noiopad
+select -assert-count 1 t:RAMB18E1
+
+# w32b | r4b
+design -reset
+read_verilog asym_ram_sdp_write_wider.v
+chparam -set WIDTHA 32 -set SIZEA 128 -set ADDRWIDTHA 7 asym_ram_sdp_read_wider
+synth_xilinx -top asym_ram_sdp_write_wider -noiopad
+select -assert-count 1 t:RAMB18E1
+
+# w4b | r24b
+design -reset
+read_verilog asym_ram_sdp_read_wider.v
+chparam -set SIZEA 768
+chparam -set WIDTHB 24 -set SIZEB 128 -set ADDRWIDTHB 7 asym_ram_sdp_read_wider
+synth_xilinx -top asym_ram_sdp_read_wider -noiopad
+select -assert-count 1 t:RAMB18E1
+
diff --git a/tests/arch/xilinx/asym_ram_sdp_read_wider.v b/tests/arch/xilinx/asym_ram_sdp_read_wider.v
new file mode 100644
index 000000000..8743209e3
--- /dev/null
+++ b/tests/arch/xilinx/asym_ram_sdp_read_wider.v
@@ -0,0 +1,72 @@
+// Asymmetric port RAM
+// Read Wider than Write. Read Statement in loop
+//asym_ram_sdp_read_wider.v
+module asym_ram_sdp_read_wider (clkA, clkB, enaA, weA, enaB, addrA, addrB, diA, doB);
+ parameter WIDTHA = 4;
+ parameter SIZEA = 1024;
+ parameter ADDRWIDTHA = 10;
+
+ parameter WIDTHB = 16;
+ parameter SIZEB = 256;
+ parameter ADDRWIDTHB = 8;
+
+ input clkA;
+ input clkB;
+ input weA;
+ input enaA, enaB;
+ input [ADDRWIDTHA-1:0] addrA;
+ input [ADDRWIDTHB-1:0] addrB;
+ input [WIDTHA-1:0] diA;
+ output [WIDTHB-1:0] doB;
+
+ `define max(a,b) {(a) > (b) ? (a) : (b)}
+ `define min(a,b) {(a) < (b) ? (a) : (b)}
+
+ function integer log2;
+ input integer value;
+ reg [31:0] shifted;
+ integer res;
+ begin
+ if (value < 2)
+ log2 = value;
+ else
+ begin
+ shifted = value-1;
+ for (res=0; shifted>0; res=res+1)
+ shifted = shifted>>1;
+ log2 = res;
+ end
+ end
+ endfunction
+
+ localparam maxSIZE = `max(SIZEA, SIZEB);
+ localparam maxWIDTH = `max(WIDTHA, WIDTHB);
+ localparam minWIDTH = `min(WIDTHA, WIDTHB);
+
+ localparam RATIO = maxWIDTH / minWIDTH;
+ localparam log2RATIO = log2(RATIO);
+
+ reg [minWIDTH-1:0] RAM [0:maxSIZE-1];
+ reg [WIDTHB-1:0] readB;
+
+ always @(posedge clkA)
+ begin
+ if (enaA) begin
+ if (weA)
+ RAM[addrA] <= diA;
+ end
+ end
+
+ always @(posedge clkB)
+ begin : ramread
+ integer i;
+ reg [log2RATIO-1:0] lsbaddr;
+ if (enaB) begin
+ for (i = 0; i < RATIO; i = i+1) begin
+ lsbaddr = i;
+ readB[(i+1)*minWIDTH-1 -: minWIDTH] <= RAM[{addrB, lsbaddr}];
+ end
+ end
+ end
+ assign doB = readB;
+endmodule \ No newline at end of file
diff --git a/tests/arch/xilinx/asym_ram_sdp_write_wider.v b/tests/arch/xilinx/asym_ram_sdp_write_wider.v
new file mode 100644
index 000000000..cd61a3ccc
--- /dev/null
+++ b/tests/arch/xilinx/asym_ram_sdp_write_wider.v
@@ -0,0 +1,71 @@
+// Asymmetric port RAM
+// Write wider than Read. Write Statement in a loop.
+// asym_ram_sdp_write_wider.v
+module asym_ram_sdp_write_wider (clkA, clkB, weA, enaA, enaB, addrA, addrB, diA, doB);
+ parameter WIDTHB = 4;
+ parameter SIZEB = 1024;
+ parameter ADDRWIDTHB = 10;
+
+ parameter WIDTHA = 16;
+ parameter SIZEA = 256;
+ parameter ADDRWIDTHA = 8;
+
+ input clkA;
+ input clkB;
+ input weA;
+ input enaA, enaB;
+ input [ADDRWIDTHA-1:0] addrA;
+ input [ADDRWIDTHB-1:0] addrB;
+ input [WIDTHA-1:0] diA;
+ output [WIDTHB-1:0] doB;
+
+ `define max(a,b) {(a) > (b) ? (a) : (b)}
+ `define min(a,b) {(a) < (b) ? (a) : (b)}
+
+ function integer log2;
+ input integer value;
+ reg [31:0] shifted;
+ integer res;
+ begin
+ if (value < 2)
+ log2 = value;
+ else
+ begin
+ shifted = value-1;
+ for (res=0; shifted>0; res=res+1)
+ shifted = shifted>>1;
+ log2 = res;
+ end
+ end
+ endfunction
+
+ localparam maxSIZE = `max(SIZEA, SIZEB);
+ localparam maxWIDTH = `max(WIDTHA, WIDTHB);
+ localparam minWIDTH = `min(WIDTHA, WIDTHB);
+
+ localparam RATIO = maxWIDTH / minWIDTH;
+ localparam log2RATIO = log2(RATIO);
+
+ reg [minWIDTH-1:0] RAM [0:maxSIZE-1];
+ reg [WIDTHB-1:0] readB;
+
+ always @(posedge clkB) begin
+ if (enaB) begin
+ readB <= RAM[addrB];
+ end
+ end
+ assign doB = readB;
+
+ always @(posedge clkA)
+ begin : ramwrite
+ integer i;
+ reg [log2RATIO-1:0] lsbaddr;
+ for (i=0; i< RATIO; i= i+ 1) begin : write1
+ lsbaddr = i;
+ if (enaA) begin
+ if (weA)
+ RAM[{addrA, lsbaddr}] <= diA[(i+1)*minWIDTH-1 -: minWIDTH];
+ end
+ end
+ end
+endmodule \ No newline at end of file
diff --git a/tests/arch/xilinx/priority_memory.v b/tests/arch/xilinx/priority_memory.v
new file mode 100644
index 000000000..fc943e209
--- /dev/null
+++ b/tests/arch/xilinx/priority_memory.v
@@ -0,0 +1,122 @@
+module priority_memory (
+ clk, wren_a, rden_a, addr_a, wdata_a, rdata_a,
+ wren_b, rden_b, addr_b, wdata_b, rdata_b
+ );
+
+ parameter ABITS = 12;
+ parameter WIDTH = 72;
+
+ input clk;
+ input wren_a, rden_a, wren_b, rden_b;
+ input [ABITS-1:0] addr_a, addr_b;
+ input [WIDTH-1:0] wdata_a, wdata_b;
+ output reg [WIDTH-1:0] rdata_a, rdata_b;
+
+ `ifdef USE_HUGE
+ (* ram_style = "huge" *)
+ `endif
+ reg [WIDTH-1:0] mem [0:2**ABITS-1];
+
+ integer i;
+ initial begin
+ rdata_a <= 'h0;
+ rdata_b <= 'h0;
+ end
+
+ `ifndef FLIP_PORTS
+ always @(posedge clk) begin
+ // A port
+ if (wren_a)
+ mem[addr_a] <= wdata_a;
+ else if (rden_a)
+ rdata_a <= mem[addr_a];
+
+ // B port
+ if (wren_b)
+ mem[addr_b] <= wdata_b;
+ else if (rden_b)
+ if (wren_a && addr_a == addr_b)
+ rdata_b <= wdata_a;
+ else
+ rdata_b <= mem[addr_b];
+ end
+ `else // FLIP PORTS
+ always @(posedge clk) begin
+ // A port
+ if (wren_b)
+ mem[addr_b] <= wdata_b;
+ else if (rden_b)
+ rdata_b <= mem[addr_b];
+
+ // B port
+ if (wren_a)
+ mem[addr_a] <= wdata_a;
+ else if (rden_a)
+ if (wren_b && addr_a == addr_b)
+ rdata_a <= wdata_b;
+ else
+ rdata_a <= mem[addr_a];
+ end
+ `endif
+endmodule
+
+module sp_write_first (clk, wren_a, rden_a, addr_a, wdata_a, rdata_a);
+
+ parameter ABITS = 12;
+ parameter WIDTH = 72;
+
+ input clk;
+ input wren_a, rden_a;
+ input [ABITS-1:0] addr_a;
+ input [WIDTH-1:0] wdata_a;
+ output reg [WIDTH-1:0] rdata_a;
+
+ (* ram_style = "huge" *)
+ reg [WIDTH-1:0] mem [0:2**ABITS-1];
+
+ integer i;
+ initial begin
+ rdata_a <= 'h0;
+ end
+
+
+ always @(posedge clk) begin
+ // A port
+ if (wren_a)
+ mem[addr_a] <= wdata_a;
+ if (rden_a)
+ if (wren_a)
+ rdata_a <= wdata_a;
+ else
+ rdata_a <= mem[addr_a];
+ end
+endmodule
+
+module sp_read_first (clk, wren_a, rden_a, addr_a, wdata_a, rdata_a);
+
+ parameter ABITS = 12;
+ parameter WIDTH = 72;
+
+ input clk;
+ input wren_a, rden_a;
+ input [ABITS-1:0] addr_a;
+ input [WIDTH-1:0] wdata_a;
+ output reg [WIDTH-1:0] rdata_a;
+
+ (* ram_style = "huge" *)
+ reg [WIDTH-1:0] mem [0:2**ABITS-1];
+
+ integer i;
+ initial begin
+ rdata_a <= 'h0;
+ end
+
+
+ always @(posedge clk) begin
+ // A port
+ if (wren_a)
+ mem[addr_a] <= wdata_a;
+ if (rden_a)
+ rdata_a <= mem[addr_a];
+ end
+endmodule
diff --git a/tests/arch/xilinx/priority_memory.ys b/tests/arch/xilinx/priority_memory.ys
new file mode 100644
index 000000000..d0b2a16ad
--- /dev/null
+++ b/tests/arch/xilinx/priority_memory.ys
@@ -0,0 +1,60 @@
+
+# no uram by default
+design -reset
+read_verilog priority_memory.v
+synth_xilinx -family xcup -top priority_memory
+select -assert-none t:URAM288
+
+# uram parameter
+design -reset
+read -define USE_HUGE
+read_verilog priority_memory.v
+synth_xilinx -family xcup -top priority_memory -noiopad
+select -assert-count 1 t:URAM288
+
+# uram option
+design -reset
+read_verilog priority_memory.v
+synth_xilinx -family xcup -top priority_memory -noiopad -uram
+# check for URAM block
+select -assert-count 1 t:URAM288
+# check port A in code maps to port A in hardware:
+# %co:+[DOUT_A] selects everything connected to a URAM288.DOUT_A port
+# w:rdata_a selects the wire rdata_a
+# %i finds the intersection of the two above selections
+# if the result is 1 then the wire rdata_a is connected to Port A correctly
+select -assert-count 1 t:URAM288 %co:+[DOUT_A] w:rdata_a %i
+# we expect no more than 2 LUT2s to control the hardware priority
+# if there are extra LUTs, then it is likely emulating logic it shouldn't
+# ignore anything using blif, since that doesn't seem to support priority logic
+# and is indicative of using verific/tabby
+select -assert-max 2 t:LUT* n:*blif* %d
+
+# reverse priority
+design -reset
+read -define FLIP_PORTS
+read_verilog priority_memory.v
+synth_xilinx -family xcup -top priority_memory -noiopad -uram
+# test priority is mapped correctly, rdata_a should now be connected to Port B
+# see above for details
+select -assert-count 1 t:URAM288 %co:+[DOUT_B] w:rdata_a %i
+
+# sp write first
+design -reset
+read_verilog priority_memory.v
+synth_xilinx -family xcup -top sp_write_first -noiopad
+select -assert-count 1 t:URAM288
+# write first connects rdata_a to port B
+# similar to above, but also tests that rdata_a *isn't* connected to port A
+select -assert-none 1 t:URAM288 %co:+[DOUT_A] w:rdata_a %i
+select -assert-count 1 t:URAM288 %co:+[DOUT_B] w:rdata_a %i
+
+# sp read first
+design -reset
+read_verilog priority_memory.v
+synth_xilinx -family xcup -top sp_read_first -noiopad
+select -assert-count 1 t:URAM288
+# read first connects rdata_a to port A
+# see above for details
+select -assert-count 1 t:URAM288 %co:+[DOUT_A] w:rdata_a %i
+select -assert-none 1 t:URAM288 %co:+[DOUT_B] w:rdata_a %i
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-09 00:45:24 +0000