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Diffstat (limited to 'tests/ice40/fsm.ys')
| -rw-r--r-- | tests/ice40/fsm.ys | 13 |
1 files changed, 0 insertions, 13 deletions
diff --git a/tests/ice40/fsm.ys b/tests/ice40/fsm.ys deleted file mode 100644 index 4cc8629d6..000000000 --- a/tests/ice40/fsm.ys +++ /dev/null @@ -1,13 +0,0 @@ -read_verilog fsm.v -hierarchy -top top -proc -flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module - -select -assert-count 2 t:SB_DFFESR -select -assert-count 2 t:SB_DFFSR -select -assert-count 1 t:SB_DFFSS -select -assert-count 13 t:SB_LUT4 -select -assert-none t:SB_DFFESR t:SB_DFFSR t:SB_DFFSS t:SB_LUT4 %% t:* %D |