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Diffstat (limited to 'tests/ice40/latches.ys')
| -rw-r--r-- | tests/ice40/latches.ys | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/tests/ice40/latches.ys b/tests/ice40/latches.ys new file mode 100644 index 000000000..f3562559e --- /dev/null +++ b/tests/ice40/latches.ys @@ -0,0 +1,15 @@ +read_verilog latches.v +design -save read + +proc +async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock +flatten +synth_ice40 +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) + +design -load read +synth_ice40 +cd top +select -assert-count 4 t:SB_LUT4 +select -assert-none t:SB_LUT4 %% t:* %D |