7 files changed, 211 insertions, 0 deletions
diff --git a/tests/memories/run-test.sh b/tests/memories/run-test.sh
index 49922e3da..b8657056a 100755
--- a/tests/memories/run-test.sh
+++ b/tests/memories/run-test.sh
@@ -23,6 +23,10 @@ for f in `egrep -l 'expect-(wr-ports|rd-ports|rd-clk)' *.v`; do
 		grep -q "parameter \\\\WR_PORTS $(gawk '/expect-wr-ports/ { print $3; }' $f)\$" ${f%.v}.dmp ||
 				{ echo " ERROR: Unexpected number of write ports."; false; }
 	fi
+	if grep -q expect-wr-wide-continuation $f; then
+		grep -q "parameter \\\\WR_WIDE_CONTINUATION $(gawk '/expect-wr-wide-continuation/ { print $3; }' $f)\$" ${f%.v}.dmp ||
+				{ echo " ERROR: Unexpected write wide continuation."; false; }
+	fi
 	if grep -q expect-rd-ports $f; then
 		grep -q "parameter \\\\RD_PORTS $(gawk '/expect-rd-ports/ { print $3; }' $f)\$" ${f%.v}.dmp ||
 				{ echo " ERROR: Unexpected number of read ports."; false; }
@@ -55,6 +59,10 @@ for f in `egrep -l 'expect-(wr-ports|rd-ports|rd-clk)' *.v`; do
 		grep -q "parameter \\\\RD_INIT_VALUE $(gawk '/expect-rd-init-val/ { print $3; }' $f)\$" ${f%.v}.dmp ||
 				{ echo " ERROR: Unexpected read init value."; false; }
 	fi
+	if grep -q expect-rd-wide-continuation $f; then
+		grep -q "parameter \\\\RD_WIDE_CONTINUATION $(gawk '/expect-rd-wide-continuation/ { print $3; }' $f)\$" ${f%.v}.dmp ||
+				{ echo " ERROR: Unexpected read wide continuation."; false; }
+	fi
 	if grep -q expect-no-rd-clk $f; then
 		grep -q "connect \\\\RD_CLK 1'x\$" ${f%.v}.dmp ||
 				{ echo " ERROR: Expected no read clock."; false; }
diff --git a/tests/memories/wide_read_async.v b/tests/memories/wide_read_async.v
new file mode 100644
index 000000000..aecdb1938
--- /dev/null
+++ b/tests/memories/wide_read_async.v
@@ -0,0 +1,27 @@
+// expect-wr-ports 1
+// expect-rd-ports 4
+// expect-rd-wide-continuation 4'1110
+
+module test(
+	input clk,
+	input we,
+	input [5:0] ra,
+	input [7:0] wa,
+	input [7:0] wd,
+	output [31:0] rd
+);
+
+reg [7:0] mem[0:255];
+
+assign rd[7:0] = mem[{ra, 2'b00}];
+assign rd[15:8] = mem[{ra, 2'b01}];
+assign rd[23:16] = mem[{ra, 2'b10}];
+assign rd[31:24] = mem[{ra, 2'b11}];
+
+always @(posedge clk) begin
+	if (we)
+		mem[wa] <= wd;
+end
+
+endmodule
+
diff --git a/tests/memories/wide_read_mixed.v b/tests/memories/wide_read_mixed.v
new file mode 100644
index 000000000..c36db3d31
--- /dev/null
+++ b/tests/memories/wide_read_mixed.v
@@ -0,0 +1,46 @@
+// expect-wr-ports 1
+// expect-rd-ports 4
+// expect-rd-wide-continuation 4'1110
+// expect-rd-srst-val 32'10000111011001010100001100100001
+// expect-rd-init-val 32'10101011110011011110111110101011
+
+// In this testcase, the byte-wide read ports are merged into a single
+// word-wide port despite mismatched transparency, with soft transparency
+// logic inserted on half the port to preserve the semantics.
+
+module test(
+	input clk,
+	input re, rr,
+	input we,
+	input [5:0] ra,
+	input [7:0] wa,
+	input [7:0] wd,
+	output reg [31:0] rd
+);
+
+reg [7:0] mem[0:255];
+
+initial rd = 32'habcdefab;
+
+always @(posedge clk) begin
+	if (rr) begin
+		rd <= 32'h87654321;
+	end else if (re) begin
+		rd[7:0] <= mem[{ra, 2'b00}];
+		rd[15:8] <= mem[{ra, 2'b01}];
+		rd[23:16] <= mem[{ra, 2'b10}];
+		rd[31:24] <= mem[{ra, 2'b11}];
+		if (we && wa == {ra, 2'b00})
+			rd [7:0] <= wd;
+		if (we && wa == {ra, 2'b01})
+			rd [15:8] <= wd;
+	end
+end
+
+always @(posedge clk) begin
+	if (we)
+		mem[wa] <= wd;
+end
+
+endmodule
+
diff --git a/tests/memories/wide_read_sync.v b/tests/memories/wide_read_sync.v
new file mode 100644
index 000000000..54ba3f256
--- /dev/null
+++ b/tests/memories/wide_read_sync.v
@@ -0,0 +1,32 @@
+// expect-wr-ports 1
+// expect-rd-ports 4
+// expect-rd-wide-continuation 4'1110
+
+module test(
+	input clk,
+	input re,
+	input we,
+	input [5:0] ra,
+	input [7:0] wa,
+	input [7:0] wd,
+	output reg [31:0] rd
+);
+
+reg [7:0] mem[0:255];
+
+always @(posedge clk) begin
+	if (re) begin
+		rd[7:0] <= mem[{ra, 2'b00}];
+		rd[15:8] <= mem[{ra, 2'b01}];
+		rd[23:16] <= mem[{ra, 2'b10}];
+		rd[31:24] <= mem[{ra, 2'b11}];
+	end
+end
+
+always @(posedge clk) begin
+	if (we)
+		mem[wa] <= wd;
+end
+
+endmodule
+
diff --git a/tests/memories/wide_read_trans.v b/tests/memories/wide_read_trans.v
new file mode 100644
index 000000000..fe3293500
--- /dev/null
+++ b/tests/memories/wide_read_trans.v
@@ -0,0 +1,40 @@
+// expect-wr-ports 1
+// expect-rd-ports 4
+// expect-rd-wide-continuation 4'1110
+
+module test(
+	input clk,
+	input re,
+	input we,
+	input [5:0] ra,
+	input [7:0] wa,
+	input [7:0] wd,
+	output reg [31:0] rd
+);
+
+reg [7:0] mem[0:255];
+
+always @(posedge clk) begin
+	if (re) begin
+		rd[7:0] <= mem[{ra, 2'b00}];
+		rd[15:8] <= mem[{ra, 2'b01}];
+		rd[23:16] <= mem[{ra, 2'b10}];
+		rd[31:24] <= mem[{ra, 2'b11}];
+		if (we && wa == {ra, 2'b00})
+			rd [7:0] <= wd;
+		if (we && wa == {ra, 2'b01})
+			rd [15:8] <= wd;
+		if (we && wa == {ra, 2'b10})
+			rd [23:16] <= wd;
+		if (we && wa == {ra, 2'b11})
+			rd [31:24] <= wd;
+	end
+end
+
+always @(posedge clk) begin
+	if (we)
+		mem[wa] <= wd;
+end
+
+endmodule
+
diff --git a/tests/memories/wide_thru_priority.v b/tests/memories/wide_thru_priority.v
new file mode 100644
index 000000000..10c0d837b
--- /dev/null
+++ b/tests/memories/wide_thru_priority.v
@@ -0,0 +1,29 @@
+// expect-wr-ports 3
+// expect-rd-ports 1
+// expect-wr-wide-continuation 3'010
+
+module test(
+	input clk,
+	input we1, we2,
+	input [5:0] ra,
+	input [4:0] wa1,
+	input [5:0] wa2,
+	input [15:0] wd1,
+	input [7:0] wd2,
+	output [7:0] rd
+);
+
+reg [7:0] mem[0:63];
+
+assign rd = mem[ra];
+
+always @(posedge clk) begin
+	if (we1)
+		mem[{wa1, 1'b0}] <= wd1[7:0];
+	if (we2)
+		mem[wa2] <= wd2;
+	if (we1)
+		mem[{wa1, 1'b1}] <= wd1[15:8];
+end
+
+endmodule
diff --git a/tests/memories/wide_write.v b/tests/memories/wide_write.v
new file mode 100644
index 000000000..5c4cc41f9
--- /dev/null
+++ b/tests/memories/wide_write.v
@@ -0,0 +1,29 @@
+// expect-wr-ports 4
+// expect-rd-ports 1
+// expect-wr-wide-continuation 4'1110
+
+module test(
+	input clk,
+	input [3:0] we,
+	input [7:0] ra,
+	input [5:0] wa,
+	input [31:0] wd,
+	output [7:0] rd
+);
+
+reg [7:0] mem[0:255];
+
+assign rd = mem[ra];
+
+always @(posedge clk) begin
+	if (we[0])
+		mem[{wa, 2'b00}] <= wd[7:0];
+	if (we[1])
+		mem[{wa, 2'b01}] <= wd[15:8];
+	if (we[2])
+		mem[{wa, 2'b10}] <= wd[23:16];
+	if (we[3])
+		mem[{wa, 2'b11}] <= wd[31:24];
+end
+
+endmodule