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Diffstat (limited to 'tests/opt/opt_expr_plus_assignment.ys')
| -rw-r--r-- | tests/opt/opt_expr_plus_assignment.ys | 15 |
1 files changed, 0 insertions, 15 deletions
diff --git a/tests/opt/opt_expr_plus_assignment.ys b/tests/opt/opt_expr_plus_assignment.ys deleted file mode 100644 index 8d8ee5214..000000000 --- a/tests/opt/opt_expr_plus_assignment.ys +++ /dev/null @@ -1,15 +0,0 @@ -read_verilog -sv <<EOT -module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o); -wire[8:0] a = 8'b0; -initial begin - a += i; - a += j; -end - assign o = a; -endmodule -EOT -proc -equiv_opt -assert opt_expr -fine -design -load postopt - -select -assert-count 1 t:$add r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i |