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Diffstat (limited to 'tests/sva/basic05.sv')
| -rw-r--r-- | tests/sva/basic05.sv | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/tests/sva/basic05.sv b/tests/sva/basic05.sv index 03854aaac..816ee1da7 100644 --- a/tests/sva/basic05.sv +++ b/tests/sva/basic05.sv @@ -11,5 +11,9 @@ module top (input logic clock, ctrl); assign ready = uut.ready; a_rw: assert property ( @(posedge clock) !(read && write) ); +`ifdef FAIL a_wr: assert property ( @(posedge clock) write |-> ready ); +`else + a_wr: assert property ( @(posedge clock) write |=> ready ); +`endif endmodule |