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-rw-r--r--tests/techmap/adff2dff.ys19
1 files changed, 19 insertions, 0 deletions
diff --git a/tests/techmap/adff2dff.ys b/tests/techmap/adff2dff.ys
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+++ b/tests/techmap/adff2dff.ys
@@ -0,0 +1,19 @@
+read_verilog -icells << EOT
+module top(...);
+
+input [1:0] D;
+input C, R;
+output [1:0] Q;
+
+always @(posedge C, posedge R)
+ if (R)
+ Q <= 0;
+ else
+ Q <= D;
+
+endmodule
+EOT
+
+proc
+
+equiv_opt -async2sync techmap -map +/adff2dff.v