1 files changed, 69 insertions, 13 deletions
diff --git a/tests/various/dynamic_part_select.ys b/tests/various/dynamic_part_select.ys
index abc1daad6..7db0f62c0 100644
--- a/tests/various/dynamic_part_select.ys
+++ b/tests/various/dynamic_part_select.ys
@@ -3,18 +3,18 @@ read_verilog ./dynamic_part_select/original.v
 proc
 rename -top gold
 design -stash gold
-
+ 
 read_verilog ./dynamic_part_select/original_gate.v
 proc
 rename -top gate
 design -stash gate
-
+ 
 design -copy-from gold -as gold gold
 design -copy-from gate -as gate gate
-
+ 
 miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
 sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv
-
+ 
 ### Multiple blocking assingments ###
 design -reset
 read_verilog ./dynamic_part_select/multiple_blocking.v
@@ -29,7 +29,7 @@ design -stash gate
  
 design -copy-from gold -as gold gold
 design -copy-from gate -as gate gate
-
+ 
 miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
 sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv
  
@@ -39,7 +39,7 @@ read_verilog ./dynamic_part_select/nonblocking.v
 proc
 rename -top gold
 design -stash gold
-
+ 
 read_verilog ./dynamic_part_select/nonblocking_gate.v
 proc
 rename -top gate
@@ -47,7 +47,7 @@ design -stash gate
  
 design -copy-from gold -as gold gold
 design -copy-from gate -as gate gate
-
+ 
 miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
 sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv
  
@@ -57,7 +57,7 @@ read_verilog ./dynamic_part_select/forloop_select.v
 proc
 rename -top gold
 design -stash gold
-
+ 
 read_verilog ./dynamic_part_select/forloop_select_gate.v
 proc
 rename -top gate
@@ -65,7 +65,7 @@ design -stash gate
  
 design -copy-from gold -as gold gold
 design -copy-from gate -as gate gate
-
+ 
 miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
 sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv
  
@@ -75,12 +75,12 @@ read_verilog ./dynamic_part_select/reset_test.v
 proc
 rename -top gold
 design -stash gold
-
+ 
 read_verilog ./dynamic_part_select/reset_test_gate.v
 proc
 rename -top gate
 design -stash gate
-
+ 
 design -copy-from gold -as gold gold
 design -copy-from gate -as gate gate
  
@@ -93,14 +93,70 @@ read_verilog ./dynamic_part_select/reversed.v
 proc
 rename -top gold
 design -stash gold
-
+ 
 read_verilog ./dynamic_part_select/reversed_gate.v
 proc
 rename -top gate
 design -stash gate
-
+ 
 design -copy-from gold -as gold gold
 design -copy-from gate -as gate gate
  
 miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
 sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv
+
+### Latches
+## Issue 1990
+design -reset
+read_verilog ./dynamic_part_select/latch_1990.v
+hierarchy -top latch_1990; prep; async2sync
+rename -top gold
+design -stash gold
+
+read_verilog ./dynamic_part_select/latch_1990_gate.v
+hierarchy -top latch_1990_gate; prep
+rename -top gate
+design -stash gate
+
+design -copy-from gold -as gold gold
+design -copy-from gate -as gate gate
+ 
+miter -equiv -make_assert -make_outcmp -flatten gold gate equiv    
+sat -prove-asserts -show-public -verify -set-init-zero equiv
+
+###
+## Part select with obvious latch, expected to fail due comparison with old shift&mask AST transformation    
+design -reset
+read_verilog ./dynamic_part_select/latch_002.v
+hierarchy -top latch_002; prep; async2sync
+rename -top gold
+design -stash gold
+
+read_verilog ./dynamic_part_select/latch_002_gate.v
+hierarchy -top latch_002_gate; prep; async2sync
+rename -top gate
+design -stash gate
+
+design -copy-from gold -as gold gold
+design -copy-from gate -as gate gate
+ 
+miter -equiv -make_assert -make_outcmp -flatten gold gate equiv    
+sat -prove-asserts -seq 10 -show-public -falsify -set-init-zero equiv
+
+## Part select + latch, with no shift&mask
+design -reset
+read_verilog ./dynamic_part_select/latch_002.v
+hierarchy -top latch_002; prep; async2sync
+rename -top gold
+design -stash gold
+
+read_verilog ./dynamic_part_select/latch_002_gate_good.v
+hierarchy -top latch_002_gate; prep; async2sync
+rename -top gate
+design -stash gate
+
+design -copy-from gold -as gold gold
+design -copy-from gate -as gate gate
+ 
+miter -equiv -make_assert -make_outcmp -flatten gold gate equiv    
+sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv