1 files changed, 39 insertions, 4 deletions
diff --git a/tests/xilinx/mux.ys b/tests/xilinx/mux.ys
index 6ecee58f5..4cdb12e47 100644
--- a/tests/xilinx/mux.ys
+++ b/tests/xilinx/mux.ys
@@ -1,10 +1,45 @@
 read_verilog mux.v
+design -save read
+
+proc
+hierarchy -top mux2
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux2 # Constrain all select calls below inside the top module
+select -assert-count 1 t:LUT3
+
+select -assert-none t:LUT3 %% t:* %D
+
+
+design -load read
 proc
-flatten
+hierarchy -top mux4
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
+cd mux4 # Constrain all select calls below inside the top module
+select -assert-count 1 t:LUT6
+
+select -assert-none t:LUT6 %% t:* %D
+
+
+design -load read
+proc
+hierarchy -top mux8
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux8 # Constrain all select calls below inside the top module
+select -assert-count 1 t:LUT3
+select -assert-count 2 t:LUT6
 
-select -assert-count 2  t:LUT3
-select -assert-count 5  t:LUT6
 select -assert-none t:LUT3 t:LUT6 %% t:* %D
+
+
+design -load read
+proc
+hierarchy -top mux16
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux16 # Constrain all select calls below inside the top module
+select -assert-count 5 t:LUT6
+
+select -assert-none t:LUT6 %% t:* %D