1 files changed, 0 insertions, 45 deletions
diff --git a/tests/xilinx/mux.ys b/tests/xilinx/mux.ys
deleted file mode 100644
index 420dece4e..000000000
--- a/tests/xilinx/mux.ys
+++ /dev/null
@@ -1,45 +0,0 @@
-read_verilog mux.v
-design -save read
-
-hierarchy -top mux2
-proc
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd mux2 # Constrain all select calls below inside the top module
-select -assert-count 1 t:LUT3
-
-select -assert-none t:LUT3 %% t:* %D
-
-
-design -load read
-hierarchy -top mux4
-proc
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd mux4 # Constrain all select calls below inside the top module
-select -assert-count 1 t:LUT6
-
-select -assert-none t:LUT6 %% t:* %D
-
-
-design -load read
-hierarchy -top mux8
-proc
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd mux8 # Constrain all select calls below inside the top module
-select -assert-count 1 t:LUT3
-select -assert-count 2 t:LUT6
-
-select -assert-none t:LUT3 t:LUT6 %% t:* %D
-
-
-design -load read
-hierarchy -top mux16
-proc
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd mux16 # Constrain all select calls below inside the top module
-select -assert-count 5 t:LUT6
-
-select -assert-none t:LUT6 %% t:* %D