1 files changed, 42 insertions, 0 deletions
diff --git a/tests/xilinx_ug901/bytewrite_ram_1b.v b/tests/xilinx_ug901/bytewrite_ram_1b.v
new file mode 100644
index 000000000..46d86c297
--- /dev/null
+++ b/tests/xilinx_ug901/bytewrite_ram_1b.v
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+// Single-Port BRAM with Byte-wide Write Enable
+// Read-First mode
+// Single-process description
+// Compact description of the write with a generate-for 
+//   statement
+// Column width and number of columns easily configurable
+//
+// bytewrite_ram_1b.v
+//
+
+module bytewrite_ram_1b (clk, we, addr, di, do);
+
+parameter SIZE = 1024; 
+parameter ADDR_WIDTH = 10; 
+parameter COL_WIDTH = 8; 
+parameter NB_COL = 4;
+
+input clk;
+input [NB_COL-1:0] we;
+input [ADDR_WIDTH-1:0] addr;
+input [NB_COL*COL_WIDTH-1:0] di;
+output reg [NB_COL*COL_WIDTH-1:0] do;
+
+reg [NB_COL*COL_WIDTH-1:0] RAM [SIZE-1:0];
+
+always @(posedge clk)
+begin
+    do <= RAM[addr];
+end
+
+generate genvar i;
+for (i = 0; i < NB_COL; i = i+1)
+begin
+always @(posedge clk)
+begin
+    if (we[i])
+        RAM[addr][(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= di[(i+1)*COL_WIDTH-1:i*COL_WIDTH];
+    end 
+end
+endgenerate
+
+endmodule