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-rw-r--r--tests/xilinx_ug901/ram_simple_dual_two_clocks.v30
1 files changed, 0 insertions, 30 deletions
diff --git a/tests/xilinx_ug901/ram_simple_dual_two_clocks.v b/tests/xilinx_ug901/ram_simple_dual_two_clocks.v
deleted file mode 100644
index 1113b928e..000000000
--- a/tests/xilinx_ug901/ram_simple_dual_two_clocks.v
+++ /dev/null
@@ -1,30 +0,0 @@
-// Simple Dual-Port Block RAM with Two Clocks
-// File: simple_dual_two_clocks.v
-
-module simple_dual_two_clocks (clka,clkb,ena,enb,wea,addra,addrb,dia,dob);
-
-input clka,clkb,ena,enb,wea;
-input [9:0] addra,addrb;
-input [15:0] dia;
-output [15:0] dob;
-reg [15:0] ram [1023:0];
-reg [15:0] dob;
-
-always @(posedge clka)
-begin
- if (ena)
- begin
- if (wea)
- ram[addra] <= dia;
- end
-end
-
-always @(posedge clkb)
-begin
- if (enb)
- begin
- dob <= ram[addrb];
- end
-end
-
-endmodule