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-rw-r--r--tests/lut/check_map_lut6.ys7
-rw-r--r--tests/lut/map_cmp.v47
-rwxr-xr-xtests/lut/run-test.sh5
-rw-r--r--tests/simple/xfirrtl4
-rw-r--r--tests/various/.gitignore2
-rw-r--r--tests/various/abc9.ys2
-rw-r--r--tests/various/gzip_verilog.v.gzbin0 -> 82 bytes
-rw-r--r--tests/various/gzip_verilog.ys2
-rw-r--r--tests/various/opt_expr.ys223
-rw-r--r--tests/various/wreduce.ys48
-rw-r--r--tests/various/write_gzip.ys16
11 files changed, 331 insertions, 25 deletions
diff --git a/tests/lut/check_map_lut6.ys b/tests/lut/check_map_lut6.ys
new file mode 100644
index 000000000..8a32e4d10
--- /dev/null
+++ b/tests/lut/check_map_lut6.ys
@@ -0,0 +1,7 @@
+chparam -set LUT_WIDTH 6 top
+simplemap
+equiv_opt -assert techmap -D LUT_WIDTH=6 -map +/cmp2lut.v
+design -load postopt
+equiv_opt -assert techmap -D LUT_WIDTH=6 -map +/gate2lut.v
+design -load postopt
+select -assert-count 0 t:* t:$lut %d
diff --git a/tests/lut/map_cmp.v b/tests/lut/map_cmp.v
index 5e413f894..0014eb9ac 100644
--- a/tests/lut/map_cmp.v
+++ b/tests/lut/map_cmp.v
@@ -1,29 +1,30 @@
module top(...);
- input [3:0] a;
+ parameter LUT_WIDTH = 4; // Multiples of 2 only
+ input [LUT_WIDTH-1:0] a;
- output o1_1 = 4'b1010 <= a;
- output o1_2 = 4'b1010 < a;
- output o1_3 = 4'b1010 >= a;
- output o1_4 = 4'b1010 > a;
- output o1_5 = 4'b1010 == a;
- output o1_6 = 4'b1010 != a;
+ output o1_1 = {(LUT_WIDTH/2){2'b10}} <= a;
+ output o1_2 = {(LUT_WIDTH/2){2'b10}} < a;
+ output o1_3 = {(LUT_WIDTH/2){2'b10}} >= a;
+ output o1_4 = {(LUT_WIDTH/2){2'b10}} > a;
+ output o1_5 = {(LUT_WIDTH/2){2'b10}} == a;
+ output o1_6 = {(LUT_WIDTH/2){2'b10}} != a;
- output o2_1 = a <= 4'b1010;
- output o2_2 = a < 4'b1010;
- output o2_3 = a >= 4'b1010;
- output o2_4 = a > 4'b1010;
- output o2_5 = a == 4'b1010;
- output o2_6 = a != 4'b1010;
+ output o2_1 = a <= {(LUT_WIDTH/2){2'b10}};
+ output o2_2 = a < {(LUT_WIDTH/2){2'b10}};
+ output o2_3 = a >= {(LUT_WIDTH/2){2'b10}};
+ output o2_4 = a > {(LUT_WIDTH/2){2'b10}};
+ output o2_5 = a == {(LUT_WIDTH/2){2'b10}};
+ output o2_6 = a != {(LUT_WIDTH/2){2'b10}};
- output o3_1 = 4'sb0101 <= $signed(a);
- output o3_2 = 4'sb0101 < $signed(a);
- output o3_3 = 4'sb0101 >= $signed(a);
- output o3_4 = 4'sb0101 > $signed(a);
- output o3_5 = 4'sb0101 == $signed(a);
- output o3_6 = 4'sb0101 != $signed(a);
+ output o3_1 = {(LUT_WIDTH/2){2'sb01}} <= $signed(a);
+ output o3_2 = {(LUT_WIDTH/2){2'sb01}} < $signed(a);
+ output o3_3 = {(LUT_WIDTH/2){2'sb01}} >= $signed(a);
+ output o3_4 = {(LUT_WIDTH/2){2'sb01}} > $signed(a);
+ output o3_5 = {(LUT_WIDTH/2){2'sb01}} == $signed(a);
+ output o3_6 = {(LUT_WIDTH/2){2'sb01}} != $signed(a);
- output o4_1 = $signed(a) <= 4'sb0000;
- output o4_2 = $signed(a) < 4'sb0000;
- output o4_3 = $signed(a) >= 4'sb0000;
- output o4_4 = $signed(a) > 4'sb0000;
+ output o4_1 = $signed(a) <= {LUT_WIDTH{1'sb0}};
+ output o4_2 = $signed(a) < {LUT_WIDTH{1'sb0}};
+ output o4_3 = $signed(a) >= {LUT_WIDTH{1'sb0}};
+ output o4_4 = $signed(a) > {LUT_WIDTH{1'sb0}};
endmodule
diff --git a/tests/lut/run-test.sh b/tests/lut/run-test.sh
index 207417fa6..f8964f146 100755
--- a/tests/lut/run-test.sh
+++ b/tests/lut/run-test.sh
@@ -4,3 +4,8 @@ for x in *.v; do
echo "Running $x.."
../../yosys -q -s check_map.ys -l ${x%.v}.log $x
done
+
+for x in map_cmp.v; do
+ echo "Running $x.."
+ ../../yosys -q -s check_map_lut6.ys -l ${x%.v}_lut6.log $x
+done
diff --git a/tests/simple/xfirrtl b/tests/simple/xfirrtl
index ba61a4476..10063d2c2 100644
--- a/tests/simple/xfirrtl
+++ b/tests/simple/xfirrtl
@@ -1,10 +1,12 @@
# This file contains the names of verilog files to exclude from verilog to FIRRTL regression tests due to known failures.
arraycells.v inst id[0] of
+defvalue.sv Initial value not supported
dff_different_styles.v
dff_init.v Initial value not supported
generate.v combinational loop
hierdefparam.v inst id[0] of
i2c_master_tests.v $adff
+implicit_ports.v not fully initialized
macros.v drops modules
mem2reg.v drops modules
mem_arst.v $adff
@@ -12,7 +14,6 @@ memory.v $adff
multiplier.v inst id[0] of
muxtree.v drops modules
omsp_dbg_uart.v $adff
-operators.v $pow
partsel.v drops modules
process.v drops modules
realexpr.v drops modules
@@ -23,5 +24,6 @@ specify.v no code (empty module generates error
subbytes.v $adff
task_func.v drops modules
values.v combinational loop
+wandwor.v Invalid connect to an expression that is not a reference or a WritePort.
vloghammer.v combinational loop
wreduce.v original verilog issues ( -x where x isn't declared signed)
diff --git a/tests/various/.gitignore b/tests/various/.gitignore
index 7b3e8c68e..31078b298 100644
--- a/tests/various/.gitignore
+++ b/tests/various/.gitignore
@@ -1,2 +1,4 @@
/*.log
/*.out
+/write_gzip.v
+/write_gzip.v.gz
diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys
index a84b637d9..5c9a4075d 100644
--- a/tests/various/abc9.ys
+++ b/tests/various/abc9.ys
@@ -19,6 +19,6 @@ hierarchy -top abc9_test028
proc
abc9 -lut 4
-select -assert-count 1 t:$lut r:LUT=1 r:WIDTH=1 %i %i
+select -assert-count 1 t:$lut r:LUT=2'b01 r:WIDTH=1 %i %i
select -assert-count 1 t:unknown
select -assert-none t:$lut t:unknown %% t: %D
diff --git a/tests/various/gzip_verilog.v.gz b/tests/various/gzip_verilog.v.gz
new file mode 100644
index 000000000..c52a95358
--- /dev/null
+++ b/tests/various/gzip_verilog.v.gz
Binary files differ
diff --git a/tests/various/gzip_verilog.ys b/tests/various/gzip_verilog.ys
new file mode 100644
index 000000000..870317e80
--- /dev/null
+++ b/tests/various/gzip_verilog.ys
@@ -0,0 +1,2 @@
+read_verilog gzip_verilog.v.gz
+select -assert-any top
diff --git a/tests/various/opt_expr.ys b/tests/various/opt_expr.ys
new file mode 100644
index 000000000..f0306efa1
--- /dev/null
+++ b/tests/various/opt_expr.ys
@@ -0,0 +1,223 @@
+
+read_verilog <<EOT
+module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
+ assign o = (i << 4) + j;
+endmodule
+EOT
+
+equiv_opt -assert opt_expr -fine
+design -load postopt
+
+select -assert-count 1 t:$add r:A_WIDTH=5 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
+
+##########
+
+# alumacc version of above
+design -reset
+read_verilog <<EOT
+module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
+ assign o = (i << 4) + j;
+endmodule
+EOT
+
+alumacc
+equiv_opt -assert opt_expr -fine
+design -load postopt
+
+select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
+
+##########
+
+design -reset
+read_verilog <<EOT
+module opt_expr_add_signed_test(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
+ assign o = (i << 4) + j;
+endmodule
+EOT
+
+equiv_opt -assert opt_expr -fine
+design -load postopt
+
+select -assert-count 1 t:$add r:A_WIDTH=5 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
+
+##########
+
+# alumacc version of above
+design -reset
+read_verilog <<EOT
+module opt_expr_add_signed_test(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
+ assign o = (i << 4) + j;
+endmodule
+EOT
+
+alumacc
+equiv_opt -assert opt_expr -fine
+design -load postopt
+
+select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
+
+##########
+
+design -reset
+read_verilog <<EOT
+module opt_expr_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o);
+ assign o = j - (i << 4);
+endmodule
+EOT
+
+equiv_opt -assert opt_expr -fine
+design -load postopt
+
+select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
+
+##########
+
+# alumacc version of above
+design -reset
+read_verilog <<EOT
+module opt_expr_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o);
+ assign o = j - (i << 4);
+endmodule
+EOT
+
+alumacc
+equiv_opt -assert opt_expr -fine
+design -load postopt
+
+dump
+select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
+
+##########
+
+design -reset
+read_verilog <<EOT
+module opt_expr_sub_signed_test1(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
+ assign o = j - (i << 4);
+endmodule
+EOT
+
+equiv_opt -assert opt_expr -fine
+design -load postopt
+
+select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
+
+##########
+
+# alumacc version of above
+design -reset
+read_verilog <<EOT
+module opt_expr_sub_signed_test1(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
+ assign o = j - (i << 4);
+endmodule
+EOT
+
+alumacc
+equiv_opt -assert opt_expr -fine
+design -load postopt
+
+select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
+
+##########
+
+design -reset
+read_verilog <<EOT
+module opt_expr_sub_test2(input [3:0] i, input [7:0] j, output [8:0] o);
+ assign o = (i << 4) - j;
+endmodule
+EOT
+
+equiv_opt -assert opt_expr -fine
+design -load postopt
+
+select -assert-count 1 t:$sub r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
+
+##########
+
+# alumacc version of above
+design -reset
+read_verilog <<EOT
+module opt_expr_sub_test2(input [3:0] i, input [7:0] j, output [8:0] o);
+ assign o = (i << 4) - j;
+endmodule
+EOT
+
+alumacc
+opt_expr -fine
+equiv_opt -assert opt_expr -fine
+design -load postopt
+
+select -assert-count 1 t:$alu r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
+
+##########
+
+design -reset
+read_verilog <<EOT
+module opt_expr_sub_test4(input [3:0] i, output [8:0] o);
+ assign o = 5'b00010 - i;
+endmodule
+EOT
+
+wreduce
+equiv_opt -assert opt_expr -fine
+design -load postopt
+
+select -assert-count 1 t:$sub r:A_WIDTH=2 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
+
+##########
+
+# alumacc version of above
+design -reset
+read_verilog <<EOT
+module opt_expr_sub_test4(input [3:0] i, output [8:0] o);
+ assign o = 5'b00010 - i;
+endmodule
+EOT
+
+wreduce
+alumacc
+equiv_opt -assert opt_expr -fine
+design -load postopt
+
+select -assert-count 1 t:$alu r:A_WIDTH=2 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
+
+###########
+
+design -reset
+read_verilog -icells <<EOT
+module opt_expr_alu_test_ci0_bi0(input [7:0] a, input [3:0] b, output [8:0] x, y, co);
+ \$alu #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(9)) alu (.A(a), .B({b, 4'b0000}), .CI(1'b0), .BI(1'b0), .X(x), .Y(y), .CO(co));
+endmodule
+EOT
+check
+
+equiv_opt -assert opt_expr -fine
+design -load postopt
+select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
+
+###########
+
+design -reset
+read_verilog -icells <<EOT
+module opt_expr_alu_test_ci1_bi1(input [7:0] a, input [3:0] b, output [8:0] x, y, co);
+ \$alu #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(9)) alu (.A(a), .B({b, 4'b0000}), .CI(1'b1), .BI(1'b1), .X(x), .Y(y), .CO(co));
+endmodule
+EOT
+check
+
+equiv_opt opt_expr -fine
+design -load postopt
+select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
+
+###########
+
+design -reset
+read_verilog -icells <<EOT
+module opt_expr_alu_test_ci0_bi1(input [7:0] a, input [3:0] b, output [8:0] x, y, co);
+ \$alu #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(9)) alu (.A(a), .B({b, 4'b0000}), .CI(1'b0), .BI(1'b1), .X(x), .Y(y), .CO(co));
+endmodule
+EOT
+check
+
+equiv_opt opt_expr -fine
+design -load postopt
+select -assert-count 1 t:$alu r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
diff --git a/tests/various/wreduce.ys b/tests/various/wreduce.ys
new file mode 100644
index 000000000..4257292f5
--- /dev/null
+++ b/tests/various/wreduce.ys
@@ -0,0 +1,48 @@
+read_verilog <<EOT
+module wreduce_sub_test(input [3:0] i, input [7:0] j, output [8:0] o);
+ assign o = (j >> 4) - i;
+endmodule
+EOT
+
+hierarchy -auto-top
+proc
+design -save gold
+
+opt_expr
+wreduce
+
+select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
+
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+##########
+
+read_verilog <<EOT
+module wreduce_sub_signed_test(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
+ assign o = (j >>> 4) - i;
+endmodule
+EOT
+
+hierarchy -auto-top
+proc
+design -save gold
+
+opt_expr
+wreduce
+
+dump
+select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
+
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
diff --git a/tests/various/write_gzip.ys b/tests/various/write_gzip.ys
new file mode 100644
index 000000000..524ecc33e
--- /dev/null
+++ b/tests/various/write_gzip.ys
@@ -0,0 +1,16 @@
+read_verilog <<EOT
+module top(input a, output y);
+assign y = !a;
+endmodule
+EOT
+
+prep -top top
+write_verilog write_gzip.v.gz
+design -reset
+
+! rm -f write_gzip.v
+! gunzip write_gzip.v.gz
+read_verilog write_gzip.v
+! rm -f write_gzip.v
+hierarchy -top top
+select -assert-any top
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-16 16:16:39 +0000