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-rw-r--r--tests/various/submod.ys4
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/various/submod.ys b/tests/various/submod.ys
index f50556d76..a0a3f2da5 100644
--- a/tests/various/submod.ys
+++ b/tests/various/submod.ys
@@ -1,8 +1,8 @@
read_verilog <<EOT
-module top(input a, output [1:0] b);
+module top(input a, output b);
wire c;
(* submod="bar" *) sub s1(a, c);
-assign b[0] = c;
+assign b = c;
endmodule
module sub(input a, output c);