diff options
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/opt/opt_expr_or_assignment.ys | 15 | ||||
| -rw-r--r-- | tests/opt/opt_expr_plus_assignment.ys | 15 |
2 files changed, 30 insertions, 0 deletions
diff --git a/tests/opt/opt_expr_or_assignment.ys b/tests/opt/opt_expr_or_assignment.ys new file mode 100644 index 000000000..21e08550f --- /dev/null +++ b/tests/opt/opt_expr_or_assignment.ys @@ -0,0 +1,15 @@ +read_verilog -sv <<EOT +module opt_expr_or_test(input [3:0] i, input [7:0] j, output [8:0] o); +wire[8:0] a = 8'b0; +initial begin + a |= i; + a |= j; +end + assign o = a; +endmodule +EOT +proc +equiv_opt -assert opt_expr -fine +design -load postopt + +select -assert-count 1 t:$or r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i diff --git a/tests/opt/opt_expr_plus_assignment.ys b/tests/opt/opt_expr_plus_assignment.ys new file mode 100644 index 000000000..8d8ee5214 --- /dev/null +++ b/tests/opt/opt_expr_plus_assignment.ys @@ -0,0 +1,15 @@ +read_verilog -sv <<EOT +module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o); +wire[8:0] a = 8'b0; +initial begin + a += i; + a += j; +end + assign o = a; +endmodule +EOT +proc +equiv_opt -assert opt_expr -fine +design -load postopt + +select -assert-count 1 t:$add r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i |