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-rw-r--r--tests/proc/.gitignore1
-rw-r--r--tests/proc/bug_1268.v23
-rw-r--r--tests/proc/bug_1268.ys5
-rwxr-xr-xtests/proc/run-test.sh6
-rw-r--r--tests/simple/realexpr.v11
-rw-r--r--tests/various/pmgen_reduce.ys21
6 files changed, 66 insertions, 1 deletions
diff --git a/tests/proc/.gitignore b/tests/proc/.gitignore
new file mode 100644
index 000000000..397b4a762
--- /dev/null
+++ b/tests/proc/.gitignore
@@ -0,0 +1 @@
+*.log
diff --git a/tests/proc/bug_1268.v b/tests/proc/bug_1268.v
new file mode 100644
index 000000000..698ac937a
--- /dev/null
+++ b/tests/proc/bug_1268.v
@@ -0,0 +1,23 @@
+module gold (input clock, ctrl, din, output reg dout);
+ always @(posedge clock) begin
+ if (1'b1) begin
+ if (1'b0) begin end else begin
+ dout <= 0;
+ end
+ if (ctrl)
+ dout <= din;
+ end
+ end
+endmodule
+
+module gate (input clock, ctrl, din, output reg dout);
+ always @(posedge clock) begin
+ if (1'b1) begin
+ if (1'b0) begin end else begin
+ dout <= 0;
+ end
+ end
+ if (ctrl)
+ dout <= din;
+ end
+endmodule
diff --git a/tests/proc/bug_1268.ys b/tests/proc/bug_1268.ys
new file mode 100644
index 000000000..b73e94449
--- /dev/null
+++ b/tests/proc/bug_1268.ys
@@ -0,0 +1,5 @@
+read_verilog bug_1268.v
+proc
+equiv_make gold gate equiv
+equiv_induct
+equiv_status -assert
diff --git a/tests/proc/run-test.sh b/tests/proc/run-test.sh
new file mode 100755
index 000000000..44ce7e674
--- /dev/null
+++ b/tests/proc/run-test.sh
@@ -0,0 +1,6 @@
+#!/bin/bash
+set -e
+for x in *.ys; do
+ echo "Running $x.."
+ ../../yosys -ql ${x%.ys}.log $x
+done
diff --git a/tests/simple/realexpr.v b/tests/simple/realexpr.v
index 5b756e6be..74ed8faa5 100644
--- a/tests/simple/realexpr.v
+++ b/tests/simple/realexpr.v
@@ -1,4 +1,3 @@
-
module demo_001(y1, y2, y3, y4);
output [7:0] y1, y2, y3, y4;
@@ -22,3 +21,13 @@ module demo_002(y0, y1, y2, y3);
assign y3 = 1 ? -1 : 'd0;
endmodule
+module demo_003(output A, B);
+ parameter real p = 0;
+ assign A = (p==1.0);
+ assign B = (p!="1.000000");
+endmodule
+
+module demo_004(output A, B, C, D);
+ demo_003 #(1.0) demo_real (A, B);
+ demo_003 #(1) demo_int (C, D);
+endmodule
diff --git a/tests/various/pmgen_reduce.ys b/tests/various/pmgen_reduce.ys
new file mode 100644
index 000000000..c214d3f25
--- /dev/null
+++ b/tests/various/pmgen_reduce.ys
@@ -0,0 +1,21 @@
+test_pmgen -generate reduce
+hierarchy -top pmtest_test_pmgen_pm_reduce
+flatten; opt_clean
+
+design -save gold
+test_pmgen -reduce_chain
+design -stash gate
+
+design -copy-from gold -as gold pmtest_test_pmgen_pm_reduce
+design -copy-from gate -as gate pmtest_test_pmgen_pm_reduce
+miter -equiv -flatten -make_assert gold gate miter
+sat -verify -prove-asserts miter
+
+design -load gold
+test_pmgen -reduce_tree
+design -stash gate
+
+design -copy-from gold -as gold pmtest_test_pmgen_pm_reduce
+design -copy-from gate -as gate pmtest_test_pmgen_pm_reduce
+miter -equiv -flatten -make_assert gold gate miter
+sat -verify -prove-asserts miter