aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
...
* | | | | | | | | | | | Fix sign handling of real constantsClifford Wolf2019-02-131-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | | | | | | Merge pull request #802 from whitequark/write_verilog_async_mem_portsClifford Wolf2019-02-121-38/+41
|\ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | write_verilog: correctly emit asynchronous transparent ports
| * | | | | | | | | | | | write_verilog: correctly emit asynchronous transparent ports.whitequark2019-01-291-38/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit fixes two related issues: * For asynchronous ports, clock is no longer added to domain list. (This would lead to absurd constructs like `always @(posedge 0)`. * The logic to distinguish synchronous and asynchronous ports is changed to correctly use or avoid clock in all cases. Before this commit, the following RTLIL snippet (after memory_collect) cell $memrd $2 parameter \MEMID "\\mem" parameter \ABITS 2 parameter \WIDTH 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 1 parameter \TRANSPARENT 1 connect \CLK 1'0 connect \EN 1'1 connect \ADDR \mem_r_addr connect \DATA \mem_r_data end would lead to invalid Verilog: reg [1:0] _0_; always @(posedge 1'h0) begin _0_ <= mem_r_addr; end assign mem_r_data = mem[_0_]; Note that there are two potential pitfalls remaining after this change: * For asynchronous ports, the \EN input and \TRANSPARENT parameter are silently ignored. (Per discussion in #760 this is the correct behavior.) * For synchronous transparent ports, the \EN input is ignored. This matches the behavior of the $mem simulation cell. Again, see #760.
* | | | | | | | | | | | | Merge pull request #806 from daveshah1/fsm_opt_no_resetClifford Wolf2019-02-121-1/+2
|\ \ \ \ \ \ \ \ \ \ \ \ \ | |_|_|_|/ / / / / / / / / |/| | | | | | | | | | | | fsm_opt: Fix runtime error for FSMs without a reset state
| * | | | | | | | | | | | fsm_opt: Fix runtime error for FSMs without a reset stateDavid Shah2019-02-071-1/+2
|/ / / / / / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | | | | * | | | | | | Missing headers for Xcode?Eddie Hung2019-02-121-0/+2
| | | | | | | | | | | |
| | | | | * | | | | | | Merge branch 'read_aiger' of github.com:eddiehung/yosys into read_aigerEddie Hung2019-02-121-3/+1
| | | | | |\ \ \ \ \ \ \
| | | | | | * | | | | | | Do not break for constraintsEddie Hung2019-02-111-1/+0
| | | | | | | | | | | | |
| | | | | | * | | | | | | No increment line_count for binary ANDsEddie Hung2019-02-111-1/+1
| | | | | | | | | | | | |
| | | | | | * | | | | | | Do not ignore newline after AND in binary AIGEddie Hung2019-02-111-1/+0
| | | | | | | | | | | | |
| | | | | * | | | | | | | Use module->add{Not,And}Gate() functionsEddie Hung2019-02-121-8/+2
| | | | | |/ / / / / / /
| | | | | * | | | | | | Merge remote-tracking branch 'origin/dff_init' into read_aigerEddie Hung2019-02-082-7/+7
| | | | | |\ \ \ \ \ \ \ | | | |_|_|/ / / / / / / | | |/| | | | | | | | / | | | | | | |_|_|_|_|/ | | | | | |/| | | | |
| | * | | | | | | | | Cope WIDTH of ff/latch cells is default of zeroEddie Hung2019-02-061-6/+6
| | | | | | | | | | |
| | * | | | | | | | | Remove check for cell->name[0] == '$'Eddie Hung2019-02-061-1/+1
| | | | | | | | | | |
| | | | | * | | | | | addDff -> addDffGate as per @daveshah1Eddie Hung2019-02-081-1/+1
| | | | | | | | | | |
| | | | | * | | | | | Fix tabulationEddie Hung2019-02-081-28/+28
| | | | | | | | | | |
| | | | | * | | | | | -module_name arg to go before -clk_nameEddie Hung2019-02-081-7/+7
| | | | | | | | | | |
| | | | | * | | | | | Support and differentiate between ASCII and binary AIG testingEddie Hung2019-02-082-2/+6
| | | | | | | | | | |
| | | | | * | | | | | Add missing "[options]" to read_blif helpEddie Hung2019-02-081-1/+1
| | | | | | | | | | |
| | | | | * | | | | | Allow module name to be determined by argument tooEddie Hung2019-02-082-14/+44
| | | | | | | | | | |
| | | | | * | | | | | Refactor into AigerReader classEddie Hung2019-02-082-79/+92
| | | | | | | | | | |
| | | | | * | | | | | Parse binary AIG filesEddie Hung2019-02-081-49/+164
| | | | | | | | | | |
| | | | | * | | | | | Add binary AIGs converted from AAGEddie Hung2019-02-0814-0/+51
| | | | | | | | | | |
| | | | | * | | | | | Refactor to parse_aiger_header()Eddie Hung2019-02-081-26/+32
| | | | | | | | | | |
| | | | | * | | | | | Add commentEddie Hung2019-02-081-0/+1
| | | | | | | | | | |
| | | | | * | | | | | Handle reset logic in latchesEddie Hung2019-02-081-2/+17
| | | | | | | | | | |
| | | | | * | | | | | Change literal vars from int to unsignedEddie Hung2019-02-081-1/+1
| | | | | | | | | | |
| | | | | * | | | | | Create clk outside of latch loopEddie Hung2019-02-081-7/+9
| | | | | | | | | | |
| | | | | * | | | | | Handle latch symbols tooEddie Hung2019-02-081-3/+1
| | | | | | | | | | |
| | | | | * | | | | | Remove return after log_errorEddie Hung2019-02-081-27/+9
| | | | | | | | | | |
| | | | | * | | | | | Add support for symbol tablesEddie Hung2019-02-081-1/+49
| | | | | | | | | | |
| | | | | * | | | | | Stub for binary AIGEREddie Hung2019-02-081-3/+8
| | | | | | | | | | |
| | | | | * | | | | | RefactorEddie Hung2019-02-061-1/+8
| | | | | | | | | | |
| | | | | * | | | | | Merge branch 'dff_init' of https://github.com/eddiehung/yosys into xaigEddie Hung2019-02-067-50/+172
| | | | | |\ \ \ \ \ \ | | | |_|_|/ / / / / / | | |/| | | | | | | |
| | * | | | | | | | | RefactorEddie Hung2019-02-061-21/+5
| | | | | | | | | | |
| | * | | | | | | | | write_verilog to cope with init attr on q when -noexprEddie Hung2019-02-061-2/+32
| | | | | | | | | | |
| | * | | | | | | | | Add INIT parameter to all ff/latch cellsEddie Hung2019-02-062-43/+86
| | | | | | | | | | |
| | * | | | | | | | | Add tests for simple cases using defparamEddie Hung2019-02-061-0/+21
| | | | | | | | | | |
| | * | | | | | | | | Add -B option to autotest.sh to append to backend_optsEddie Hung2019-02-061-2/+4
| | | | | | | | | | |
| | * | | | | | | | | Extend testcaseEddie Hung2019-02-061-2/+34
| | | | | | | | | | |
| | * | | | | | | | | Add testcaseEddie Hung2019-02-061-0/+10
| |/ / / / / / / / / |/| | | | | | | | |
* | | | | | | | | | Add missing blackslash-to-slash convertion to smtio.py (matching ↵Clifford Wolf2019-02-061-1/+1
|/ / / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Smt2Worker::get_id() behavior) Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | | * | | | | | Revert most of autotest.sh; for non *.v use Yosys to translateEddie Hung2019-02-061-7/+9
| | | | | | | | |
| | | * | | | | | Rename ASCII testsEddie Hung2019-02-0615-0/+0
| | | | | | | | |
| | | * | | | | | WIPEddie Hung2019-02-063-0/+247
| | | | | | | | |
| | | * | | | | | Add testsEddie Hung2019-02-0416-8/+109
| |_|/ / / / / / |/| | | | | | |
* | | | | | | | Merge pull request #798 from mmicko/masterClifford Wolf2019-01-271-1/+1
|\ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | Fixed Anlogic simulation model
| * | | | | | | | Fixed Anlogic simulation modelMiodrag Milanovic2019-01-251-1/+1
| | |/ / / / / / | |/| | | | | |
* | | | | | | | Merge pull request #800 from whitequark/write_verilog_tribufClifford Wolf2019-01-271-0/+12
|\ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | write_verilog: write $tribuf cell as ternary
| * | | | | | | | write_verilog: write $tribuf cell as ternary.whitequark2019-01-271-0/+12
| | | | | | | | |