| Commit message (Collapse) | Author | Age | Files | Lines | |
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| * | Merge pull request #3734 from jix/fix_unbased_unsized_constHEADmaster | Jannis Harder | 2023-04-24 | 3 | -1/+36 |
| |\ | | | | | verilog: Fix const eval of unbased unsized constants | ||||
| | * | verilog: Fix const eval of unbased unsized constants | Jannis Harder | 2023-04-20 | 3 | -1/+36 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the verilog frontend perfomed constant evaluation of unbased unsized constants in a context-determined expression it did not properly extend them by repeating the bit value. This only affected constant evaluation and not constants that made it through unchanged to RTLIL. The latter case was already covered by tests and working before. This fixes the const-eval issue by checking the `is_unsized` flag in bitsAsConst and extending the value accordingly. The newly added test also tests the already working non-const-eval case to highlight that both cases should behave the same. | ||||
| * | | Bump version | github-actions[bot] | 2023-04-23 | 1 | -1/+1 |
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| * | | ABC9: Cell Port Bug Patch (#3670) | Benjamin Barzen | 2023-04-22 | 4 | -2/+26 |
| |/ | | | | | | | | | | | | | | | | | * ABC9: RAMB36E1 Bug Patch * Add simplified testcase * Also fix xaiger writer for under-width output ports * Remove old testcase * Missing top-level input port * Fix tabs --------- Co-authored-by: Eddie Hung <eddie@fpgeh.com> | ||||
| * | Bump version | github-actions[bot] | 2023-04-19 | 1 | -1/+1 |
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| * | Merge pull request #3732 from hzeller/20230417-remote-statement-no-effect | Jannis Harder | 2023-04-18 | 1 | -2/+0 |
| |\ | | | | | Remove a statement without effect. | ||||
| | * | Remove a statement without effect. | Henner Zeller | 2023-04-17 | 1 | -2/+0 |
| |/ | | | | | | | The return value of the min(...) call is never used. Looks like some leftover from some previous implementation. Signed-off-by: Henner Zeller <h.zeller@acm.org> | ||||
| * | Bump version | github-actions[bot] | 2023-04-15 | 1 | -1/+1 |
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| * | Next dev cycle | Miodrag Milanovic | 2023-04-14 | 2 | -2/+5 |
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| * | Release version 0.28 | Miodrag Milanovic | 2023-04-14 | 2 | -3/+14 |
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| * | Merge pull request #3727 from YosysHQ/micko/pll_bram | Miodrag Milanović | 2023-04-14 | 5 | -124/+325 |
| |\ | | | | | MachXO2: Add PLL and EBR related primitives | ||||
| | * | Add PLL and EBR related primitives | Miodrag Milanovic | 2023-04-10 | 5 | -124/+325 |
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| * | | Bump version | github-actions[bot] | 2023-04-13 | 1 | -1/+1 |
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| * | | fabulous: Add support for LUT6s | gatecat | 2023-04-12 | 2 | -1/+38 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | | gowin: Add serialization/deserialization primitives | YRabbit | 2023-04-12 | 1 | -0/+244 |
| | | | | | | | | | | | | | | | | | Primitives are added to convert parallel signals to serial and vice versa. IDES4, IDES8, IDES10, IDES16, IVIDEO, OSER4, OSER8, OSER10, OSER16, OVIDEO. Signed-off-by: YRabbit <rabbit@yrabbit.cyou> | ||||
| * | | Bump version | github-actions[bot] | 2023-04-07 | 1 | -1/+1 |
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| * | ecp5: Remove TRELLIS_SLICE and add TRELLIS_COMB model | gatecat | 2023-04-06 | 1 | -160/+30 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | add additional dff and lutram tests | Miodrag Milanovic | 2023-04-06 | 2 | -0/+57 |
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| * | add test for CCU2D | Miodrag Milanovic | 2023-04-06 | 1 | -0/+10 |
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| * | Add more DFF types | Miodrag Milanovic | 2023-04-06 | 5 | -48/+102 |
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| * | Added proper simulation model for CCU2D | Miodrag Milanovic | 2023-04-06 | 1 | -15/+35 |
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| * | Generate TRELLIS_DPR16X4 for lutram | Miodrag Milanovic | 2023-04-06 | 3 | -21/+72 |
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| * | machxo2: Initial support for carry chains (CCU2D) | Miodrag Milanovic | 2023-04-06 | 4 | -5/+127 |
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| * | Bump version | github-actions[bot] | 2023-03-24 | 1 | -1/+1 |
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| * | Update Xilinx cell definitions, fixes #3699 | Miodrag Milanovic | 2023-03-23 | 3 | -6/+16 |
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| * | Bump version | github-actions[bot] | 2023-03-21 | 1 | -1/+1 |
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| * | Merge pull request #3708 from jix/void_func | Jannis Harder | 2023-03-20 | 3 | -1/+56 |
| |\ | | | | | verilog: Support void functions | ||||
| | * | verilog: Support void functions | Jannis Harder | 2023-03-20 | 3 | -1/+56 |
| |/ | | | | | | | The difference between void functions and tasks is that always_comb's implicit sensitivity list behaves as if functions were inlined, but ignores signals read only in tasks. This only matters for event based simulation, and for synthesis we can treat a void function like a task. | ||||
| * | Update tests | Miodrag Milanovic | 2023-03-20 | 7 | -16/+16 |
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| * | Start unification effort for machxo2 and ecp5 | Miodrag Milanovic | 2023-03-20 | 4 | -31/+23 |
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| * | Add additional iopad_external_pin attributes | Miodrag Milanovic | 2023-03-20 | 1 | -4/+22 |
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| * | Add iopad_external_pin to some basic io primitives | Miodrag Milanovic | 2023-03-20 | 2 | -12/+13 |
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| * | insert IO buffers for ECP5, off by default | Miodrag Milanovic | 2023-03-20 | 1 | -1/+14 |
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| * | Bump version | github-actions[bot] | 2023-03-16 | 1 | -1/+1 |
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| * | Merge pull request #3704 from jix/enum_values | Miodrag Milanović | 2023-03-15 | 3 | -34/+89 |
| |\ | | | | | verific: Fix enum_values support and signed attribute values | ||||
| | * | verific: Fix enum_values support and signed attribute values | Jannis Harder | 2023-03-15 | 3 | -34/+89 |
| | | | | | | | | | | | | | This uses the same constant parsing for enum_values and for attributes and extends it to handle signed values as those are used for enums that implicitly use the int type. | ||||
| * | | Bump version | github-actions[bot] | 2023-03-11 | 1 | -1/+1 |
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| * | Merge pull request #3682 from daglem/struct-member-out-of-bounds | Jannis Harder | 2023-03-10 | 8 | -22/+145 |
| |\ | | | | | Out of bounds checking for struct/union members | ||||
| | * | Added test for dynamic indexing within struct members | Dag Lem | 2023-03-08 | 2 | -0/+71 |
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| | * | Index struct/union members within corresponding wire chunks | Dag Lem | 2023-03-05 | 5 | -33/+69 |
| | | | | | | | | | | | This guards against access to bits outside of struct/union members via dynamic indexing. | ||||
| | * | Out of bounds checking for struct/union members | Dag Lem | 2023-02-19 | 3 | -6/+22 |
| | | | | | | | | | Currently, only constant indices are checked. | ||||
| * | | ice40: Fix path delay definitions | Stefan Riesenberger | 2023-03-10 | 1 | -14/+14 |
| | | | | | | | | | | | | | Parallel connections do not allow matching different bit widths. A full connection has to be used instead. Allows iverilog to parse the simulation library with hardware path delays enabled. | ||||
| * | | Bump version | github-actions[bot] | 2023-03-07 | 1 | -1/+1 |
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| * | | Merge pull request #3684 from YosysHQ/fix-GIT_REV | N. Engelhardt | 2023-03-06 | 1 | -1/+1 |
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| | * | | Makefile: fix GIT_REV extraction if Yosys is built as submodule. | Catherine | 2023-03-01 | 1 | -1/+1 |
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| * | | | Next dev cycle | Miodrag Milanovic | 2023-03-06 | 2 | -2/+5 |
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| * | | | Release version 0.27 | Miodrag Milanovic | 2023-03-06 | 2 | -3/+14 |
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| * | | | Bump version | github-actions[bot] | 2023-03-02 | 1 | -1/+1 |
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| * | | | Merge pull request #3690 from whitequark/smtbmc-help-opt | N. Engelhardt | 2023-03-01 | 1 | -4/+13 |
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| | * | | | yosys-smtbmc: support -h/--help (and exit with code 0). | Catherine | 2023-02-27 | 1 | -4/+13 |
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