| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | | | Add "#ifdef __FreeBSD__" | Christian Krämer | 2018-05-13 | 5 | -9/+52 | |
| | | | | | | | | | | | | | (Re-commit e3575a8 with corrected author field) | |||||
| * | | | Revert "Add "#ifdef __FreeBSD__"" | Clifford Wolf | 2018-05-13 | 5 | -52/+9 | |
| | | | | | | | | | | | | | This reverts commit e3575a86c525f2511902e7022893c3923ba8093e. | |||||
| * | | | Also interpret '&' in liberty functions | Sergiusz Bazanski | 2018-05-12 | 1 | -1/+1 | |
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| * | | | Add optimization of tristate buffer with constant control input | Clifford Wolf | 2018-05-12 | 1 | -0/+17 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Add "hierarchy -simcheck" | Clifford Wolf | 2018-05-12 | 1 | -7/+23 | |
| |/ / | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Further improve handling of zero-length SVA consecutive repetition | Clifford Wolf | 2018-05-05 | 1 | -69/+108 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Fix handling of zero-length SVA consecutive repetition | Clifford Wolf | 2018-05-05 | 1 | -26/+46 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Add "#ifdef __FreeBSD__" | Johnny Sorocil | 2018-05-05 | 5 | -9/+52 | |
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| * | | Add ABC FAQ to "help abc" | Clifford Wolf | 2018-05-04 | 1 | -2/+6 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Add "yosys -e regex" for turning warnings into errors | Clifford Wolf | 2018-05-04 | 3 | -4/+22 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Merge pull request #537 from mithro/yosys-vpr | Clifford Wolf | 2018-05-04 | 4 | -11/+48 | |
| |\ \ | | | | | | | Improving Yosys when used with VPR | |||||
| | * | | Improving vpr output support. | Tim 'mithro' Ansell | 2018-04-18 | 4 | -7/+40 | |
| | | | | | | | | | | | | | | | | | | | | | | * Support output BLIF for Xilinx architectures. * Support using .names in BLIF for Xilinx architectures. * Use the same `NO_LUT` define in both `synth_ice40` and `synth_xilinx`. | |||||
| | * | | synth_ice40: Rework the vpr blif output slightly. | Tim 'mithro' Ansell | 2018-04-18 | 1 | -4/+8 | |
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| * | | | Replace -ignore_redef with -[no]overwrite | Clifford Wolf | 2018-05-03 | 5 | -21/+58 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Support more character literals | Dan Gisselquist | 2018-05-03 | 1 | -1/+9 | |
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| * | | | Update ABC to git rev f23ea8e | Clifford Wolf | 2018-04-30 | 1 | -1/+1 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Add "synth_intel --noiopads" | Clifford Wolf | 2018-04-30 | 1 | -2/+11 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Add $dlatch support to write_verilog | Clifford Wolf | 2018-04-22 | 1 | -0/+38 | |
| |/ / | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Add "synth_ice40 -nodffe" | Clifford Wolf | 2018-04-16 | 1 | -2/+11 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Add "write_blif -inames -iattr" | Clifford Wolf | 2018-04-15 | 1 | -22/+46 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Add statement labels for immediate assertions | Clifford Wolf | 2018-04-13 | 1 | -18/+21 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Allow "property" in immediate assertions | Clifford Wolf | 2018-04-12 | 1 | -17/+20 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Improve Makefile error handling for when abc/ is a hg working copy | Clifford Wolf | 2018-04-12 | 1 | -0/+3 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Add PRIM_HDL_ASSERTION support to Verific importer | Clifford Wolf | 2018-04-07 | 1 | -3/+19 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Fix handling of $global_clocking in Verific | Clifford Wolf | 2018-04-06 | 1 | -1/+7 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Add documentation for anyconst/anyseq/allconst/allseq attribute | Clifford Wolf | 2018-04-06 | 1 | -0/+4 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Add read_verilog anyseq/anyconst/allseq/allconst attribute support | Clifford Wolf | 2018-04-06 | 1 | -1/+33 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Add Verific anyseq/anyconst/allseq/allconst attribute support | Clifford Wolf | 2018-04-06 | 1 | -2/+36 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Add "verific -autocover" | Clifford Wolf | 2018-04-06 | 2 | -5/+17 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Merge pull request #530 from makaimann/set-ram-flags | Clifford Wolf | 2018-04-06 | 1 | -0/+3 | |
| |\ \ | | | | | | | Set RAM runtime flags for Verific frontend | |||||
| | * | | Set RAM runtime flags for Verific frontend | makaimann | 2018-04-05 | 1 | -0/+3 | |
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| * | | Added missing dont_use handling for SR FFs to dfflibmap | Clifford Wolf | 2018-04-05 | 1 | -0/+4 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Create issue_template.md | Clifford Wolf | 2018-04-04 | 1 | -0/+16 | |
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| * | | Add smtio.py support for parsing SMT2 (_ bvX n) syntax for BitVec constants | Clifford Wolf | 2018-04-04 | 1 | -0/+3 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Fixed -stbv handling in SMT2 back-end | Clifford Wolf | 2018-04-04 | 1 | -1/+1 | |
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| * | | Merge pull request #522 from c60k28/master | Clifford Wolf | 2018-04-01 | 11 | -178/+233 | |
| |\ \ | | | | | | | Fixed broken Quartus backend on dffeas init value, and other updates. | |||||
| | * | | Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal ↵ | c60k28 | 2018-03-31 | 11 | -178/+233 | |
| |/ / | | | | | | | value for the POWER_UP parameter. Fixed and tested Cyclone V device | |||||
| * | | Remove left-over log_ping debug commands.. oops. | Clifford Wolf | 2018-03-31 | 1 | -4/+0 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Merge pull request #521 from azonenberg/for_clifford | Clifford Wolf | 2018-03-31 | 4 | -0/+113 | |
| |\ \ | | | | | | | coolrunner2: Improve optimization for TFF/counters | |||||
| | * | | coolrunner2: Add an ANDTERM/XOR between chained FFs | Robert Ou | 2018-03-31 | 1 | -0/+58 | |
| | | | | | | | | | | | | | | | | | | | | | | In some cases (e.g. the low bits of counters) the design might end up with a flip-flop whose input is directly driven by another flip-flop. This isn't possible in the Coolrunner-II architecture, so add a single AND term and XOR in this case. | |||||
| | * | | coolrunner2: Split multi-bit nets | Robert Ou | 2018-03-31 | 1 | -0/+1 | |
| | | | | | | | | | | | | | | | | The PAR tool doesn't expect any "dangling" nets with no drivers nor sinks. By splitting the nets, clean removes them. | |||||
| | * | | coolrunner2: Add extraction for TFFs | Robert Ou | 2018-03-31 | 3 | -0/+54 | |
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| * | | Add smtio status msgs when --progress is inactive | Clifford Wolf | 2018-03-29 | 1 | -2/+23 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Bugfix in smtio.py VCD file generator | Clifford Wolf | 2018-03-29 | 1 | -1/+1 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Removed $timescale from "sat" command VCD writer | Clifford Wolf | 2018-03-29 | 1 | -1/+0 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Set stack size to at least 128 MB (large stack needed for parsing huge ↵ | Clifford Wolf | 2018-03-27 | 1 | -0/+13 | |
| | | | | | | | | | | | | | expressions) Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Fix tests/simple/specify.v | Clifford Wolf | 2018-03-27 | 1 | -2/+2 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | First draft of Verilog parser support for specify blocks and parameters. | Udi Finkelstein | 2018-03-27 | 3 | -2/+201 | |
| | | | | | | | | | | | The only functionality of this code at the moment is to accept correct specify syntax and ignore it. No part of the specify block is added to the AST | |||||
| * | | Merge pull request #515 from edcote/patch-1 | Clifford Wolf | 2018-03-27 | 1 | -3/+5 | |
| |\ \ | | | | | | | Rename rename to renames | |||||
| | * | | Rename rename to renames | Edmond Cote | 2018-03-20 | 1 | -3/+5 | |
| | | | | | | | | | | Create TCL alias for rename command. Using renames. Following the same convention as proc -> procs. | |||||
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