| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | | Fixed more visual studio warnings | Clifford Wolf | 2016-02-14 | 1 | -5/+3 | |
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| * | | Fixed some visual studio warnings | Clifford Wolf | 2016-02-13 | 8 | -10/+10 | |
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| * | | Merge branch 'master' of github.com:cliffordwolf/yosys | Clifford Wolf | 2016-02-13 | 1 | -1/+1 | |
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| | * | | Fixed MXE ABC build | Clifford Wolf | 2016-02-13 | 1 | -1/+1 | |
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| * | | | Added "int ceil_log2(int)" function | Clifford Wolf | 2016-02-13 | 5 | -10/+58 | |
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| * | | Run dffsr2dff in synth_xilinx | Clifford Wolf | 2016-02-13 | 1 | -0/+2 | |
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| * | | Support for more Verific primitives (patch I got per email) | Clifford Wolf | 2016-02-13 | 1 | -1/+31 | |
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| * | | Updated ABC | Clifford Wolf | 2016-02-08 | 1 | -1/+1 | |
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| * | | Work around DDR dout sim glitches in ice40 SB_IO sim model | Clifford Wolf | 2016-02-07 | 1 | -1/+7 | |
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| * | | Updated ABC | Clifford Wolf | 2016-02-07 | 1 | -1/+1 | |
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| * | | Added "stat -liberty" for calculating chip area | Clifford Wolf | 2016-02-04 | 1 | -6/+60 | |
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| * | | Bugfix in Verific front-end | Clifford Wolf | 2016-02-03 | 1 | -2/+5 | |
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| * | | Updated verific build instructions | Clifford Wolf | 2016-02-02 | 1 | -2/+0 | |
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| * | | Improved dffsr2dff pass | Clifford Wolf | 2016-02-02 | 1 | -5/+50 | |
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| * | | Added dffsr2dff | Clifford Wolf | 2016-02-02 | 3 | -0/+171 | |
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| * | | Added addBufGate module method | Clifford Wolf | 2016-02-02 | 3 | -0/+8 | |
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| * | | Use alphanumerical order instead of idstring idx in opt_clean compare_signals() | Clifford Wolf | 2016-02-02 | 1 | -1/+1 | |
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| * | | Added CodeOfConduct | Clifford Wolf | 2016-02-01 | 1 | -0/+73 | |
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| * | | Updated ABC to hg rev ee212a9e94df | Clifford Wolf | 2016-02-01 | 1 | -1/+1 | |
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| * | | Progress in cell library documentation | Clifford Wolf | 2016-02-01 | 1 | -0/+238 | |
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| * | | Added "abc -luts" option, Improved Xilinx logic mapping | Clifford Wolf | 2016-02-01 | 2 | -15/+39 | |
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| * | | Improvements in dfflibmap (FFs with Q/QN outputs, DFFs from ADFFs) | Clifford Wolf | 2016-02-01 | 1 | -8/+68 | |
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| * | | SigMap performance improvement | Clifford Wolf | 2016-02-01 | 1 | -1/+7 | |
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| * | | hashlib mfp<> performance improvements | Clifford Wolf | 2016-02-01 | 1 | -2/+7 | |
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| * | | Added reserve() method to haslib classes and | Clifford Wolf | 2016-01-31 | 1 | -2/+6 | |
| | | | | | | | | | calculate hashtable size based on entries capacity, not size | |||||
| * | | Merge branch 'rtlil_remove2_speedup' of https://github.com/kc8apf/yosys | Clifford Wolf | 2016-01-31 | 2 | -14/+88 | |
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| | * | | rtlil: Improve performance of SigSpec::extract(SigSpec, SigSpec*) | Rick Altherr | 2016-01-31 | 1 | -2/+31 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | Converting to a pool<SigBit> is fairly expensive due to inserts somewhat frequently causing rehashing. Instead, walk through the pattern SigSpec directly on a chunk-by-chunk basis and apply it to this SigSpec's individual bits. Using chunks for the pattern minimizes the number of iterations in the outer loop. | |||||
| | * | | rtlil: speed up SigSpec::sort_and_unify() | Rick Altherr | 2016-01-31 | 1 | -1/+11 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | std::set<> internally is often a red-black tree which is fairly expensive to create but fast to lookup. In the case of sort_and_unify(), a set<> is constructed as a temporary object to attempt to speed up lookups. Being a temporarily, however, the cost of creation far outweights the lookup improvement and is a net performance loss. Instead, sort the vector<> that already exists and then apply std::unique(). | |||||
| | * | | rtlil: improve performance of SigSpec::replace(SigSpec, SigSpec, SigSpec*) | Rick Altherr | 2016-01-31 | 1 | -6/+14 | |
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| | * | | genrtlil: avoid converting SigSpec to set<SigBit> when going through ↵ | Rick Altherr | 2016-01-31 | 1 | -3/+3 | |
| | | | | | | | | | | | | | removeSignalFromCaseTree() | |||||
| | * | | rtlil: improve performance of SigSpec::remove2(SigSpec, SigSpec*) | Rick Altherr | 2016-01-31 | 1 | -2/+29 | |
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| * | | | More clang sanitizer stuff | Clifford Wolf | 2016-01-31 | 2 | -3/+12 | |
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| * | | Meaningless coding style change | Clifford Wolf | 2016-01-31 | 1 | -1/+0 | |
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| * | | Merge branch 'rtlil_remove2_speedup' of https://github.com/kc8apf/yosys | Clifford Wolf | 2016-01-31 | 2 | -23/+37 | |
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| | * | | rtlil: rewrite remove2() to avoid copying | Rick Altherr | 2016-01-30 | 1 | -45/+18 | |
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| | * | | rtlil: duplicate remove2() for std::set<> | Rick Altherr | 2016-01-29 | 2 | -0/+41 | |
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| | * | | rtlil: change IdString comparison operators to take references instead of copies | Rick Altherr | 2016-01-29 | 1 | -3/+3 | |
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| * | | | Addedd clang sanitizers | Clifford Wolf | 2016-01-31 | 1 | -0/+21 | |
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| * | | Added "equiv_struct -fwonly" | Clifford Wolf | 2016-01-08 | 1 | -5/+17 | |
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| * | | Bugfixes in equiv_struct | Clifford Wolf | 2016-01-08 | 1 | -2/+9 | |
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| * | | Added "submod -copy" | Clifford Wolf | 2016-01-08 | 1 | -13/+28 | |
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| * | | Added "write_blif -cname" mode | Clifford Wolf | 2016-01-06 | 1 | -1/+12 | |
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| * | | Added "equiv_struct -maxiter <N>" | Clifford Wolf | 2016-01-06 | 1 | -4/+16 | |
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| * | | Added "equiv_add -try" mode | Clifford Wolf | 2016-01-06 | 1 | -6/+33 | |
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| * | | Fixed "splitnets -ports" for hierarchical designs | Clifford Wolf | 2015-12-22 | 1 | -0/+57 | |
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| * | | Re-run ice40_opt in "synth_ice40 -abc2" | Clifford Wolf | 2015-12-22 | 1 | -1/+4 | |
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| * | | Improvements in ice40_opt | Clifford Wolf | 2015-12-22 | 1 | -5/+16 | |
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| * | | Bugfix in ice40_ffinit | Clifford Wolf | 2015-12-22 | 1 | -2/+2 | |
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| * | | Improved ice40_ffinit | Clifford Wolf | 2015-12-22 | 1 | -1/+22 | |
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| * | | Run opt_const before check in default scripts | Clifford Wolf | 2015-12-22 | 2 | -0/+4 | |
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index : iCE40/yosys | |
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