| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | | Use "verilog -sv" to parse .sv files | Clifford Wolf | 2014-07-11 | 1 | -0/+2 | |
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| * | | Fixed processing of initial values for block-local variables | Clifford Wolf | 2014-07-11 | 1 | -0/+5 | |
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| * | | now ignore init attributes on non-register wires in sat command | Clifford Wolf | 2014-07-05 | 3 | -4/+43 | |
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| * | | fixed parsing of constant with comment between size and value | Clifford Wolf | 2014-07-02 | 2 | -0/+14 | |
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| * | | small changes in presentation | Clifford Wolf | 2014-07-02 | 1 | -5/+2 | |
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| * | | Tiny fix in presentation | Clifford Wolf | 2014-06-29 | 1 | -1/+1 | |
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| * | | Progress in presentation | Clifford Wolf | 2014-06-29 | 2 | -0/+97 | |
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| * | | Added links to some liberty files to README | Clifford Wolf | 2014-06-28 | 1 | -0/+8 | |
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| * | | Progress in presentation | Clifford Wolf | 2014-06-26 | 7 | -79/+105 | |
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| * | | Fixed handling of mixed real/int ternary expressions | Clifford Wolf | 2014-06-25 | 2 | -3/+22 | |
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| * | | More found_real-related fixes to AstNode::detectSignWidthWorker | Clifford Wolf | 2014-06-24 | 1 | -6/+6 | |
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| * | | Progress in presentation | Clifford Wolf | 2014-06-22 | 7 | -42/+503 | |
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| * | | Little steps in realmath test bench | Clifford Wolf | 2014-06-21 | 2 | -2/+8 | |
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| * | | fixed signdness detection for expressions with reals | Clifford Wolf | 2014-06-21 | 1 | -2/+8 | |
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| * | | fixed typo | Clifford Wolf | 2014-06-21 | 1 | -1/+1 | |
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| * | | Progress in presentation | Clifford Wolf | 2014-06-21 | 9 | -23/+188 | |
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| * | | Do not create $dffsr cells with no-op resets in proc_dff | Clifford Wolf | 2014-06-19 | 1 | -0/+5 | |
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| * | | Added test case for AstNode::MEM2REG_FL_CMPLX_LHS | Clifford Wolf | 2014-06-17 | 1 | -0/+12 | |
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| * | | Added AstNode::MEM2REG_FL_CMPLX_LHS | Clifford Wolf | 2014-06-17 | 2 | -0/+23 | |
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| * | | Improved handling of relational op of real values | Clifford Wolf | 2014-06-17 | 2 | -12/+17 | |
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| * | | Little steps in realmath test bench | Clifford Wolf | 2014-06-16 | 2 | -0/+3 | |
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| * | | Improved ternary support for real values | Clifford Wolf | 2014-06-16 | 1 | -13/+24 | |
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| * | | Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012 | Clifford Wolf | 2014-06-16 | 2 | -0/+11 | |
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| * | | Fixed parsing of TOK_INTEGER (implies TOK_SIGNED) | Clifford Wolf | 2014-06-16 | 1 | -5/+11 | |
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| * | | Added found_real feature to AstNode::detectSignWidth | Clifford Wolf | 2014-06-16 | 2 | -6/+11 | |
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| * | | Added more calls to "hierarchy" to README file | Clifford Wolf | 2014-06-15 | 1 | -3/+8 | |
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| * | | Removed long running tests from tests/simple/realexpr.v (replaced by ↵ | Clifford Wolf | 2014-06-15 | 1 | -55/+0 | |
| | | | | | | | | | tests/realmath) | |||||
| * | | Added tests/realmath to "make test" | Clifford Wolf | 2014-06-15 | 5 | -4/+6 | |
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| * | | Improved AstNode::realAsConst for large numbers | Clifford Wolf | 2014-06-15 | 1 | -1/+1 | |
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| * | | Improved realmath test bench | Clifford Wolf | 2014-06-15 | 2 | -5/+13 | |
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| * | | Improved parsing of large integer constants | Clifford Wolf | 2014-06-15 | 1 | -11/+28 | |
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| * | | Improved AstNode::asReal for large integers | Clifford Wolf | 2014-06-15 | 2 | -10/+13 | |
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| * | | improved realmath test bench | Clifford Wolf | 2014-06-14 | 1 | -1/+4 | |
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| * | | improved (fixed) conversion of real values to bit vectors | Clifford Wolf | 2014-06-14 | 4 | -11/+30 | |
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| * | | progress in realmath test bench | Clifford Wolf | 2014-06-14 | 2 | -4/+45 | |
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| * | | Fixed relational operators for const real expressions | Clifford Wolf | 2014-06-14 | 1 | -8/+8 | |
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| * | | added first draft of real math testcase generator | Clifford Wolf | 2014-06-14 | 1 | -0/+52 | |
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| * | | Progress in presentation | Clifford Wolf | 2014-06-14 | 5 | -3/+109 | |
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| * | | Added %D and %c select commands | Clifford Wolf | 2014-06-14 | 1 | -2/+20 | |
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| * | | Added support for math functions | Clifford Wolf | 2014-06-14 | 2 | -0/+127 | |
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| * | | Added realexpr.v test case | Clifford Wolf | 2014-06-14 | 1 | -0/+13 | |
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| * | | Added handling of real-valued parameters/localparams | Clifford Wolf | 2014-06-14 | 4 | -24/+62 | |
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| * | | Implemented more real arithmetic | Clifford Wolf | 2014-06-14 | 1 | -27/+70 | |
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| * | | Implemented basic real arithmetic | Clifford Wolf | 2014-06-14 | 3 | -6/+51 | |
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| * | | Added real->int convertion in ast genrtlil | Clifford Wolf | 2014-06-14 | 1 | -0/+12 | |
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| * | | Added Verilog lexer and parser support for real values | Clifford Wolf | 2014-06-13 | 4 | -3/+31 | |
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| * | | Added read_verilog -sv options, added support for bit, logic, | Clifford Wolf | 2014-06-12 | 7 | -8/+52 | |
| | | | | | | | | | allways_ff, always_comb, and always_latch | |||||
| * | | Now we are in Yoys 0.3.0+ development | Clifford Wolf | 2014-06-08 | 2 | -1/+7 | |
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| * | | Tagging Yosys 0.3.0 | Clifford Wolf | 2014-06-08 | 2 | -3/+47 | |
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| * | | Updated ABC to 7600ffb9340c | Clifford Wolf | 2014-06-08 | 1 | -1/+1 | |
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index : iCE40/yosys | |
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