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* Add support for the Bitwuzla solverGCHQDeveloper5602021-07-121-5/+5
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* kernel/mem: Use delayed removal for inits as well.Marcelina Kościelnicka2021-07-122-4/+20
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* kernel/mem: Add documentation for more helper functions.Marcelina Kościelnicka2021-07-121-0/+34
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* cxxrtl: Support memory writes in processes.Marcelina Kościelnicka2021-07-121-6/+55
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* cxxrtl: Add support for memory read port reset.Marcelina Kościelnicka2021-07-121-1/+41
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* cxxrtl: Add support for mem read port initial data.Marcelina Kościelnicka2021-07-121-4/+22
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* cxxrtl: Convert to Mem helpers.Marcelina Kościelnicka2021-07-121-206/+276
| | | | | This *only* does conversion, but doesn't add any new functionality — support for memory read port init/reset is still upcoming.
* kernel/mem: Commit new values of attributes in emit.Marcelina Kościelnicka2021-07-121-0/+4
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* kernel/mem: Make the Mem helpers inherit from AttrObject.Marcelina Kościelnicka2021-07-121-8/+4
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* rtlil: Make Process handling more uniform with Cell and Wire.Marcelina Kościelnicka2021-07-128-25/+62
| | | | | | - add a backlink to module from Process - make constructor and destructor protected, expose Module functions to add and remove processes
* ice40: Fix LUT input indices in opt_lut -dlogic (again).Marcelina Kościelnicka2021-07-101-1/+1
| | | | Fixes #2061.
* Update to latest Verific with extensions for initial assertionsMiodrag Milanovic2021-07-092-15/+10
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* sv: fix a few struct and enum memory leaksZachary Snow2021-07-062-2/+11
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* ecp5: Add DCSC blackboxgatecat2021-07-061-0/+10
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #2835 from YosysHQ/verific_commandClaire Xen2021-07-051-0/+61
|\ | | | | Support command files in Verific
| * Add additional helpMiodrag Milanovic2021-07-051-0/+22
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| * Support command files in VerificMiodrag Milanovic2021-06-161-0/+39
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* | Makefile: allow running multiple sanitizers at onceXiretza2021-07-051-3/+3
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* | Makefile: use git/make -C instead of cdXiretza2021-07-051-3/+3
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* | Makefile: pass PRETTY=0 to ABCXiretza2021-07-051-1/+1
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* | Makefile: don't bake DESTDIR into libyosys DT_SONAMEXiretza2021-07-051-2/+2
| | | | | | | | | | | | DESTDIR is only used as a temporary destination for installed files before they are packaged into an archive; the "real" installed location is determined by PREFIX/{BIN,LIB,DAT}DIR.
* | Makefile: clean up PYOSYS configurationXiretza2021-07-051-34/+10
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* | Merge pull request #2842 from whitequark/fix-wasi-buildwhitequark2021-06-191-1/+1
|\ \ | | | | | | Fix WASI build after commit 1d88bea1
| * | Fix WASI build after commit 1d88bea1.whitequark2021-06-191-1/+1
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* | Merge pull request #2836 from YosysHQ/gatecat/pyosys-sigintMiodrag Milanović2021-06-181-0/+2
|\ \ | | | | | | pyosys: Clear SIGINT handler after Python loads
| * | pyosys: Clear SIGINT handler after Python loadsgatecat2021-06-161-0/+2
| |/ | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Move interface expansion in hierarchy.cc into a helper classRupert Swarbrick2021-06-161-100/+189
| | | | | | | | | | | | | | | | | | | | | | | | There should be no functional change, but this splits up the control flow across functions, using class fields to hold the state that's being tracked. The result should be a bit easier to read. This is part of work to add bind support, but I'm doing some refactoring in the hierarchy pass to make the code a bit easier to work with. The idea is that (eventually) the IFExpander object will hold all the logic for expanding interfaces, and then other code can do bind insertion.
* | sv: fix up end label checkingZachary Snow2021-06-167-7/+98
| | | | | | | | | | | | | | - disallow [gen]blocks with an end label but not begin label - check validity of module end label - fix memory leak of package name and end label - fix memory leak of module end label
* | Include blif reader header in public facing extension header files.Ashton Snelgrove2021-06-161-0/+1
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* verilog: fix leaking of type names in parserXiretza2021-06-141-0/+2
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* verilog: fix wildcard port connections leaking memoryXiretza2021-06-141-0/+1
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* ast: delete wires and localparams after finishing const evaluationXiretza2021-06-141-0/+8
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* verilog: fix leaking ASTNodesXiretza2021-06-142-7/+15
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* ast: fix error condition causing assert to failXiretza2021-06-141-2/+1
| | | | | type2str returns a string that doesn't start with $ or \, so it can't be assigned to an IdString.
* macos: fix leak in proc_self_dirname()Zachary Snow2021-06-141-1/+3
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* Simplify some RTLIL destructorsRupert Swarbrick2021-06-141-10/+10
| | | | | No change in behaviour, but use range-based for loops instead of iterators.
* verilog: Squash a memory leak.Marcelina Kościelnicka2021-06-144-19/+14
| | | | That was added in ecc22f7fedfa639482dbc55a05709da85116a60f
* Add regression test for #2824.Marcelina Kościelnicka2021-06-111-0/+7
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* opt_muxtree: Update port_off and port_idx even for constant bitsgatecat2021-06-111-17/+16
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* opt_expr: Fix mul/div/mod by POT patterns to support >= 32 bits.Marcelina Kościelnicka2021-06-093-122/+120
| | | | | The previous code, in addition to being needlessly limitted to 32 bits in the first place, also had UB for the 31th bit (doing 1 << 31).
* opt_expr: Optimize div/mod by const 1.Marcelina Kościelnicka2021-06-091-4/+4
| | | | | | | | Turns out the code for div by a power of 2 is already almost capable of optimizing this to a shift-by-0 or and-with-0, which will be further folded into nothingness; let's beef it up to handle div by 1 as well. Fixes #2820.
* Merge pull request #2817 from YosysHQ/claire/fixemailsClaire Xen2021-06-09325-1308/+1311
|\ | | | | Fixing old e-mail addresses and deadnames
| * Fix deadname SVN linksClaire Xenia Wolf2021-06-092-3/+3
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
| * Intersynth URLClaire Xenia Wolf2021-06-092-2/+2
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
| * More deadname stuffClaire Xenia Wolf2021-06-092-4/+4
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
| * Fix icestorm linksClaire Xenia Wolf2021-06-092-516/+516
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
| * More deadname stuffClaire Xenia Wolf2021-06-0910-27/+27
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| * Use HTTPS for website links, gatecat emailClaire Xenia Wolf2021-06-0920-26/+26
| | | | | | | | | | | | | | | | | | | | git ls-tree -r --name-only HEAD | xargs sed -i -rf ~/fixemails.sed s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+(Shah|gatecat)\s+<(dave|david|gatecat)@(symbioticeda.com|yosyshq.com|ds0.me)>/gatecat <gatecat@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/|http://yosyshq.net/yosys/,https://yosyshq.net/yosys/,g;
| * Fix files with CRLF line endingsClaire Xenia Wolf2021-06-095-422/+422
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| * Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-08309-331/+330
| | | | | | | | | | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
generated by cgit v1.2.3 (git 2.25.1) at 2025-07-30 20:58:15 +0000