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* intel_alm: Documentation improvementsDan Ravensloft2020-04-213-14/+127
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* write_json: dump default parameter valuesMarcelina Kościelnicka2020-04-211-0/+10
| | | | | | | | Fixes #1823. This will allow nextpnr to reuse the default value information already present in yosys cells_sim.v and avoid duplicating (and probably desyncing) this information.
* Use default parameter value in getParamMarcelina Kościelnicka2020-04-212-4/+13
| | | | Fixes #1822.
* hierarchy: Convert positional parameters to named.Marcelina Kościelnicka2020-04-212-3/+50
| | | | Fixes #1821.
* ilang, ast: Store parameter order and default value information.Marcelina Kościelnicka2020-04-216-9/+27
| | | | Fixes #1819, #1820.
* idict: Make iterator go forward.Marcelina Kościelnicka2020-04-211-5/+19
| | | | Previously, iterating over an idict returned its contents in reverse.
* Merge pull request #1971 from YosysHQ/claire/edifkeepClaire Wolf2020-04-211-14/+108
|\ | | | | Ignore conflicting keep attributes, unless asked not to
| * Improve net priorities in EDIF back-endClaire Wolf2020-04-211-0/+64
| | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
| * Ignore conflicting keep attributes, unless asked not to. Fixes #1733Claire Wolf2020-04-201-14/+44
| | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | Merge pull request #1851 from YosysHQ/claire/bitselwriteClaire Wolf2020-04-2117-15/+1431
|\ \ | | | | | | Improved rewrite code for writing to bit slice
| * \ Merge pull request #1975 from dh73/claire/bitselwriteEddie Hung2020-04-2013-0/+1224
| |\ \ | | | | | | | | Adding tests to Claire/bitselwrite branch
| | * | Remove '-ignore_unknown_cells' option from 'sat'Eddie Hung2020-04-201-6/+6
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| | * | Simplify test case scriptEddie Hung2020-04-201-30/+17
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| | * | Remove ununsed filesEddie Hung2020-04-205-83/+0
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| | * | Modifications of tests as per Eddie's requestdiego2020-04-2015-78/+1237
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| | * | Wrong fixed valuediego2020-04-171-1/+1
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| | * | Adding tests for dynamic part select optimisationdiego2020-04-167-0/+161
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| * | Make mask-and-shift the default for bitselwriteClaire Wolf2020-04-161-1/+1
| | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
| * | Add LookaheadRewriter for proper bitselwrite supportClaire Wolf2020-04-164-4/+144
| | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
| * | Improved rewrite code for writing to bit slice (disabled for now)Claire Wolf2020-04-151-12/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the new rewrite rule. But it's still missing a check that makes sure the new rewrite rule is actually a valid substitute in the always block being processed. Therefore the new rewrite rule is just disabled for now. Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | | Merge pull request #1961 from whitequark/paramod-original-namewhitequark2020-04-213-11/+7
|\ \ \ | | | | | | | | ast, rpc: record original name of $paramod\* as \hdlname attribute
| * | | ast, rpc: record original name of $paramod\* as \hdlname attribute.whitequark2020-04-183-11/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The $paramod name mangling is not invertible (the \ character, which separates the module name from the parameters, is valid in the module name itself), which does not stop people from trying to invert it. This commit makes it easy to invert the name mangling by storing the original name explicitly, and fixes the firrtl backend to use the newly introduced attribute.
* | | | tests: remove write_ilangEddie Hung2020-04-202-3/+0
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* | | | Merge pull request #1972 from YosysHQ/eddie/bug1970Eddie Hung2020-04-202-16/+52
|\ \ \ \ | |_|_|/ |/| | | abc9_ops: -prep_lut to be more robust
| * | | abc9: -prep_lut to be more robustEddie Hung2020-04-201-16/+33
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| * | | abc9: add testcase reduced from #1970Eddie Hung2020-04-201-0/+19
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* | | Merge pull request #1964 from YosysHQ/claire/sformatfClaire Wolf2020-04-201-8/+38
|\ \ \ | | | | | | | | Extend support for format strings in Verilog front-end
| * | | Extend support for format strings in Verilog front-endClaire Wolf2020-04-181-8/+38
| | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | | | Merge pull request #1967 from whitequark/cxxrtl-blackbox-attributeswhitequark2020-04-192-49/+57
|\ \ \ \ | |/ / / |/| | | cxxrtl: provide attributes to black box factories, too
| * | | cxxrtl: provide attributes to black box factories, too.whitequark2020-04-192-49/+57
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | Both parameters and attributes are necessary because the parameters have to be the same between every instantiation of the cell, but attributes may well vary. For example, for an UART PHY, the type of the PHY (tty, pty, socket) would be a parameter, but configuration of the implementation specified by the type (socket address) would be an attribute.
* | | Merge pull request #1963 from whitequark/cxxrtl-blackboxeswhitequark2020-04-182-198/+637
|\ \ \ | | | | | | | | cxxrtl: add support for simple and templated C++ black boxes
| * | | cxxrtl: add templated black box support.whitequark2020-04-181-16/+193
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| * | | cxxrtl: make eval() and commit() inline in blackboxes.whitequark2020-04-181-82/+103
| | | | | | | | | | | | | | | | | | | | This change is a preparation for template blackboxes. It has no effect on current generated code.
| * | | cxxrtl: add simple black box support.whitequark2020-04-182-70/+311
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds support for replacing RTLIL modules with CXXRTL black boxes. Black box port widths may not depend on the parameters with which it is instantiated (yet); the parameters may only be used to change the behavior of the black box.
| * | | cxxrtl: use ID::X instead of ID(X). NFC.whitequark2020-04-181-107/+107
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* | | Merge pull request #1955 from whitequark/cxxrtl-sync_alwayswhitequark2020-04-171-3/+13
|\ \ \ | | | | | | | | cxxrtl: correctly handle `sync always` rules
| * | | cxxrtl: correctly handle `sync always` rules.whitequark2020-04-171-3/+13
| |/ / | | | | | | | | | Fixes #1948.
* | | Merge pull request #1952 from boqwxp/add_edge_locationwhitequark2020-04-171-0/+3
|\ \ \ | |/ / |/| | Verilog frontend: add source location in more parser rules
| * | Set Verilog source location for explicit blocks (`begin` ... `end`).Alberto Gonzalez2020-04-171-0/+1
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| * | Add Verilog source location information to `AST_POSEDGE` and `AST_NEGEDGE` ↵Alberto Gonzalez2020-04-171-0/+2
| | | | | | | | | | | | nodes.
* | | Merge pull request #1954 from YosysHQ/dave/fix-stdout-conflictwhitequark2020-04-171-3/+3
|\ \ \ | | | | | | | | qbfsat: Fix illegal use of 'stdout' identifier
| * | | qbfsat: Fix illegal use of 'stdout' identifierDavid Shah2020-04-171-3/+3
| |/ / | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | Merge pull request #1951 from whitequark/rtlil-string_attributewhitequark2020-04-172-19/+33
|\ \ \ | |/ / |/| | rtlil: add AttrObject::{get,set}_string_attribute, AttrObject::has_attribute
| * | rtlil: add AttrObject::has_attribute.whitequark2020-04-162-0/+7
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| * | rtlil: add AttrObject::{get,set}_string_attribute.whitequark2020-04-162-19/+26
| | | | | | | | | | | | And make {get,set}_src_attribute use those functions.
* | | Merge pull request #1898 from boqwxp/locationswhitequark2020-04-171-0/+3
|\ \ \ | | | | | | | | Verilog frontend: add location information to parsed constants
| * | | Add location information to `AST_CONSTANT` nodes.Alberto Gonzalez2020-04-161-0/+3
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* | | | Merge pull request #1864 from boqwxp/cleanup_techmap_abcwhitequark2020-04-171-99/+80
|\ \ \ \ | | | | | | | | | | Clean up pseudo-private member usage and simplify `passes/techmap/abc.cc`
| * | | | Simplify `passes/techmap/abc.cc` and remove superfluous `RTLIL::SigSpec` ↵Alberto Gonzalez2020-04-141-132/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | constructions. Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
| * | | | Clean up pseudo-private member usage and simplify `passes/techmap/abc.cc`.Alberto Gonzalez2020-04-051-99/+163
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