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* Add flooring modulo operatorXiretza2020-05-2823-37/+280
| | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $modfloor cell provides this flooring modulo (also known as "remainder" in several languages, but this name is ambiguous). This commit also fixes the handling of $mod in opt_expr, which was previously optimized as if it was $modfloor.
* Merge pull request #2095 from rswarbrick/hier-typowhitequark2020-05-281-2/+2
|\ | | | | Fix small typos in documentation for hierarchy command
| * Fix small typos in documentation for hierarchy commandRupert Swarbrick2020-05-281-2/+2
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* | Merge pull request #2091 from boqwxp/printattrswhitequark2020-05-283-0/+105
|\ \ | |/ |/| Add `printattrs` command to print attributes of currently selected objects.
| * printattrs: Simplify `get_indent_str()`.Alberto Gonzalez2020-05-281-3/+1
| | | | | | | | Co-Authored-By: Xiretza <xiretza@xiretza.xyz>
| * printattrs: Refactor indentation string building for clarity.Alberto Gonzalez2020-05-271-5/+11
| | | | | | | | Co-Authored-By: whitequark <whitequark@whitequark.org>
| * printattrs: Add test.Alberto Gonzalez2020-05-271-0/+14
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| * printattrs: Use `flags` to pretty-print the `RTLIL::Const` appropriately.Alberto Gonzalez2020-05-271-8/+15
| | | | | | | | Co-Authored-By: whitequark <whitequark@whitequark.org>
| * misc: Add `printattrs` command.Alberto Gonzalez2020-05-272-0/+80
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* | Merge pull request #2051 from Xiretza/makefile-cd-warningwhitequark2020-05-281-1/+1
|\ \ | | | | | | Suppress warning during initial clone of ABC repo
| * | Suppress warning during initial clone of ABC repoXiretza2020-05-141-1/+1
| | | | | | | | | | | | | | | | | | | | | 9dedac50 introduced this harmless but disconcerting warning, which was emitted when abc/ did not yet exist and was about to be cloned: /bin/sh: line 0: cd: abc: No such file or directory
* | | Merge pull request #2031 from epfl-vlsc/masterwhitequark2020-05-281-1/+40
|\ \ \ | | | | | | | | Add extmodule support to firrtl backend
| * | | Formatting fixesSahand Kashani2020-05-061-14/+7
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| * | | Add extmodule support to firrtl backendSahand Kashani2020-05-061-1/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current firrtl backend emits blackboxes as standard modules with an empty body, but this causes the firrtl compiler to optimize out entire circuits due to the absence of any drivers. Yosys already tags blackboxes with a (*blackbox*) attribute, so this commit just propagates this change to firrtl's syntax for blackboxes.
* | | | Merge pull request #2063 from boqwxp/techmapped-firrtlwhitequark2020-05-281-10/+12
|\ \ \ \ | | | | | | | | | | firrtl: Accept techmapped cell types in FIRRTL backend.
| * | | | firrtl: Accept techmapped cell types in FIRRTL backend.Alberto Gonzalez2020-05-171-10/+12
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* | | | | Merge pull request #2088 from rswarbrick/count-atwhitequark2020-05-281-2/+8
|\ \ \ \ \ | | | | | | | | | | | | Minor optimisation in Module::wire() and Module::cell()
| * | | | | Minor optimisation in Module::wire() and Module::cell()Rupert Swarbrick2020-05-261-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The existing code does a search to figure out whether id is in the dict (with the call to count()), and then looks it up again to get the result (with the call to at()). This version calls find() instead, avoiding the double lookup. Code size increases slightly (6kb). I think this is because the contents of find() are getting inlined, and then inlined into lots of the callsites for cell() and wire(). Looking at the compiled code before this patch, you just get a (non-inlined) call to count() followed by a call to at(). After the patch, the contents of find() have been inlined (so you see do_hash, then do_lookup). The result for each function is about 30 bytes / 40% bigger, which presumably also enlarges call-sites that inline it.
* | | | | | Merge pull request #2087 from rswarbrick/lex-warnwhitequark2020-05-281-1/+3
|\ \ \ \ \ \ | | | | | | | | | | | | | | Silence spurious warning in Verilog lexer when compiling with GCC
| * | | | | | Silence spurious warning in Verilog lexer when compiling with GCCRupert Swarbrick2020-05-261-1/+3
| |/ / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The chosen value shouldn't have any effect. I considered something clearly wrong like -1, but there's no checking inside the generated lexer, and I suspect this will cause even weirder bugs if triggered than just setting it to INITIAL.
* | | | | | Merge pull request #2086 from rswarbrick/sigbitwhitequark2020-05-281-2/+1
|\ \ \ \ \ \ | | | | | | | | | | | | | | Use default copy constructor for RTLIL::SigBit
| * | | | | | Use default copy constructor for RTLIL::SigBitRupert Swarbrick2020-05-261-2/+1
| |/ / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There was a handwritten copy constructor, which I'm not sure was actually legal C++ (it unconditionally read from the 'data' member of a union, which wouldn't have been written if wire was true). It was also a bit less efficient than the constructor you get from the compiler by default (which is allowed to just copy the memory). This gives a marginal (~0.25%) decrease in code size when compiled with GCC 9.3.
* | | | | | Merge pull request #2084 from rswarbrick/c_strwhitequark2020-05-281-2/+2
|\ \ \ \ \ \ | | | | | | | | | | | | | | Use c_str(), not str() for IdString/std::string == and != operators
| * | | | | | Use c_str(), not str() for IdString/std::string == and != operatorsRupert Swarbrick2020-05-261-2/+2
| |/ / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These operators work by fetching the string from the global string table and then comparing with the std::string that was passed in as rhs. Using str() means that we create a std::string (strlen; malloc; memcpy), compare for equality (another memcmp if they have the same length) and then finally free the string. Using c_str() means that we pass the const char* straight to std::string's equality operator. This ends up as a call to std::string::compare (the const char* flavour), which is essentially strcmp.
* | | | | | Merge pull request #2090 from whitequark/cxxrtl-fixeswhitequark2020-05-261-7/+13
|\ \ \ \ \ \ | |/ / / / / |/| | | | | Minor fixes for CXXRTL
| * | | | | cxxrtl: make logging a little bit nicer.whitequark2020-05-261-2/+10
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| * | | | | cxxrtl: add missing parts of commit 281c9685.whitequark2020-05-261-5/+3
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* | | | | Merge pull request #2078 from YosysHQ/eddie/xilinx_sim_tidyEddie Hung2020-05-253-13/+15
|\ \ \ \ \ | |/ / / / |/| | | | xilinx: tidy up cells_sim.v a little
| * | | | tests: xilinx macc test to have initval, shorten BMC depth for runtimeEddie Hung2020-05-252-8/+8
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| * | | | xilinx: tidy up cells_sim.v a littleEddie Hung2020-05-251-5/+7
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* | | | | Merge pull request #2044 from YosysHQ/eddie/fix2037Eddie Hung2020-05-252-20/+85
|\ \ \ \ \ | |/ / / / |/| | | | verilog: allow attributes on behavioural statements (including null statement)
| * | | | verilog: move attr from simple_behav_stmt to its children to attachEddie Hung2020-05-251-13/+17
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| * | | | test: add attribute-before-stmt test from @nakengelhardtEddie Hung2020-05-251-0/+15
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| * | | | verilog: do not warn for attributes on null statementsEddie Hung2020-05-252-6/+4
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| * | | | tests: add an generate-else test tooEddie Hung2020-05-251-0/+34
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| * | | | verilog: handle empty generate statement by removing gen_stmt_or_null...Eddie Hung2020-05-251-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | ... rule which causes a s/r conflict. Now we get an empty genblock, which should be okay.
| * | | | verilog: fix #2037 by permitting (and freeing) attributes on null stmtEddie Hung2020-05-251-1/+5
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| * | | | tests: add #2037 testcaseEddie Hung2020-05-251-0/+9
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* | | | Merge pull request #2015 from boqwxp/qbfsat-bisectionclairexen2020-05-251-98/+207
|\ \ \ \ | | | | | | | | | | qbfsat: Add an iterative bisection optimization method and make it the default.
| * | | | qbfsat: Remove cruft inadvertently left untouched in commit ↵Alberto Gonzalez2020-05-231-11/+0
| | | | | | | | | | | | | | | | | | | | 86fc49a9d60f9ad4cdeec93663e7245a9fdf60c6.
| * | | | qbfsat: Add bisection mode and make it the default.Alberto Gonzalez2020-05-231-87/+207
| | |/ / | |/| | | | | | | | | | Also adds `-nooptimize` and reorganizes `qbfsat.cc` a bit.
* | | | Merge pull request #2075 from YosysHQ/eddie/xaiger_cleanupEddie Hung2020-05-242-7/+14
|\ \ \ \ | | | | | | | | | | xaiger: do not derive cells
| * | | | xaiger: add testcaseEddie Hung2020-05-241-0/+13
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| * | | | xaiger: do not derive cellsEddie Hung2020-05-241-7/+1
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* | | | | Merge pull request #2074 from YosysHQ/eddie/ecp5_cleanupEddie Hung2020-05-233-14/+0
|\ \ \ \ \ | |/ / / / |/| | | | ecp5: cleanup unused +/ecp5/abc9_model.v
| * | | | ecp5: cleanup unused +/ecp5/abc9_model.vEddie Hung2020-05-233-14/+0
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* | | | Merge pull request #2072 from whitequark/cxxrtl-dont-purgewhitequark2020-05-221-8/+2
|\ \ \ \ | | | | | | | | | | cxxrtl: get rid of -O5 aka `opt_clean -purge` optimization level
| * | | | cxxrtl: get rid of -O5 aka `opt_clean -purge` optimization level.whitequark2020-05-221-8/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This isn't actually necessary anymore after scheduling was improved, and `clean -purge` disrupts the mapping between wires in the input RTLIL netlist and the output CXXRTL code.
* | | | | abc9_ops: update commentEddie Hung2020-05-211-1/+1
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* | | | | Merge pull request #2057 from YosysHQ/eddie/fix_task_attrEddie Hung2020-05-212-11/+37
|\ \ \ \ \ | | | | | | | | | | | | verilog: support attributes before (not after) task identifier (but 13 s/r conflicts)
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