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* | | | | | Merge pull request #2195 from YosysHQ/mwk/manual-gatesclairexen2020-07-021-50/+201
|\ \ \ \ \ \ | |_|/ / / / |/| | | | | Add a few more gate types to the manual.
| * | | | | Add latches to the manual.Marcelina Kościelnicka2020-06-261-42/+165
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| * | | | | Add a few more gate types to the manual.Marcelina Kościelnicka2020-06-261-8/+36
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* | | | | | Merge pull request #2203 from antmicro/fix-grammarclairexen2020-07-012-4/+38
|\ \ \ \ \ \ | | | | | | | | | | | | | | Signed and macro grammar update
| * | | | | | Add signed/unsigned testsKamil Rakoczy2020-06-261-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
| * | | | | | Parse macro call attached semicolon as empty expressionLukasz Dalek2020-06-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
| * | | | | | Fix integer signing grammarLukasz Dalek2020-06-261-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit fixes signed/unsigned grammar in parameters as defined in SV LRM A2.2.1. Example of correct parameters: parameter integer signed i = 0; parameter integer unsigned i = 0; Example of incorrect parameters: parameter signed integer i = 0; parameter unsigned integer i = 0; Signed-off-by: Lukasz Dalek <ldalek@antmicro.com> Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* | | | | | | Merge pull request #2179 from splhack/static-castclairexen2020-07-0111-0/+135
|\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | Support SystemVerilog Static Cast
| * | | | | | | static cast: simplifyKazuki Sakamoto2020-06-191-0/+7
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| * | | | | | | static cast: add testsKazuki Sakamoto2020-06-195-0/+80
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| * | | | | | | static cast: support changing size and signednessKazuki Sakamoto2020-06-196-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support SystemVerilog Static Cast - size - signedness - (type is not supposted yet) Fix #535
* | | | | | | | Merge pull request #2138 from boqwxp/qbfsat-oflagclairexen2020-07-011-16/+47
|\ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | qbfsat: Add `-O[012]` options to control pre-solving simplification with ABC
| * | | | | | | | qbfsat: Add `-O[012]` options to control pre-solving simplification with ABC.Alberto Gonzalez2020-06-301-16/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Thanks to @mwk for the gate mapping part of the ABC scripts. Co-Authored-By: Marcelina Kościelnicka <mwk@0x04.net>
* | | | | | | | | Merge pull request #2206 from boqwxp/qbfsat-fix-name-specializationclairexen2020-07-011-2/+24
|\ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | qbfsat: Fix name-based hole specialization
| * | | | | | | | | qbfsat: Fix name-based hole specialization.Alberto Gonzalez2020-06-301-2/+24
| |/ / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | Look for unique connections in the containing module with the $anyconst port Y SigBit on the RHS and use those. If no such connection is found, fall back to using the name of the $anyconst port Y SigBit.
* | | | | | | | | Merge pull request #2136 from zachjs/masterclairexen2020-06-303-1/+81
|\ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | Allow constant function calls in for loops and generate if and case
| * | | | | | | | | Allow constant function calls in for loops and generate if and caseZachary Snow2020-06-293-1/+81
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* | | | | | | | | Merge pull request #2199 from YosysHQ/mmicko/sim_memoryclairexen2020-06-301-1/+4
|\ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | sim - error when memrd and memwr detected
| * | | | | | | | | sim - error when memrd and memwr detectedMiodrag Milanovic2020-06-291-1/+4
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* | | | | | | | | | Merge pull request #2201 from YosysHQ/fix_test_cell_ilangclairexen2020-06-301-2/+2
|\ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | Use ID macro to fix assertion
| * | | | | | | | | | Use ID macro to fix assertionMiodrag Milanovic2020-06-291-2/+2
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* | | | | | | | | | Merge pull request #2209 from YosysHQ/verific_updateclairexen2020-06-301-1/+1
|\ \ \ \ \ \ \ \ \ \ | |_|_|_|_|_|/ / / / |/| | | | | | | | | Update verific API version check
| * | | | | | | | | Update verific API version checkMiodrag Milanovic2020-06-301-1/+1
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* | | | | | | | | | simcells: Fix reset polarity for $_DLATCH_???_ cells.Marcelina Kościelnicka2020-06-302-5/+5
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* | | | | | | | | Merge pull request #2205 from whitequark/fix-2204whitequark2020-06-301-2/+3
|\ \ \ \ \ \ \ \ \ | |_|/ / / / / / / |/| | | | | | | | techmap: don't drop attributes on replaced cells
| * | | | | | | | techmap: don't drop attributes on replaced cells.whitequark2020-06-291-2/+3
|/ / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was introduced in 76c4ee4ea5cb6a3dc214f66237af22a1bedda010. Fixes #2204.
* | | | | | | | Merge pull request #2200 from YosysHQ/mmicko/fix_exposeMiodrag Milanović2020-06-291-7/+23
|\ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | expose pass fix
| * | | | | | | | Give error that options are exclusiveMiodrag Milanovic2020-06-291-2/+6
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| * | | | | | | | cleanupMiodrag Milanovic2020-06-291-12/+13
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| * | | | | | | | expose pass fixMiodrag Milanovic2020-06-291-5/+16
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* | | | | | | | Merge pull request #2197 from Xiretza/test_cell-shiftswhitequark2020-06-291-0/+4
|\ \ \ \ \ \ \ \ | |/ / / / / / / |/| | | | | | | test_cell: don't generate directional shifts with \B_SIGNED=1
| * | | | | | | test_cell: don't generate directional shifts with \B_SIGNED=1Xiretza2020-06-281-0/+4
|/ / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was made an explicit error in e97e33d, "kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr.".
* | | / / / / Fix crash in verific frontendMiodrag Milanovic2020-06-261-1/+2
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* | | | | | Merge pull request #2193 from whitequark/cxxrtl-help-textwhitequark2020-06-261-2/+2
|\ \ \ \ \ \ | | | | | | | | | | | | | | cxxrtl: update help text
| * | | | | | cxxrtl: update help text.whitequark2020-06-261-2/+2
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* | | | | | Merge pull request #2188 from antmicro/missing-operatorswhitequark2020-06-263-2/+132
|\ \ \ \ \ \ | | | | | | | | | | | | | | Add logic-assignments operators
| * | | | | | Add sub-assign and and-assign testsKamil Rakoczy2020-06-251-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
| * | | | | | Move combined assign tests to single fileKamil Rakoczy2020-06-254-45/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
| * | | | | | Support missing sub-assign and and-assign operatorsKamil Rakoczy2020-06-252-2/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
| * | | | | | Add xor-assignment testKamil Rakoczy2020-06-241-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
| * | | | | | Support missing xor-assign operatorLukasz Dalek2020-06-242-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
| * | | | | | Add or-assignment and plus-assignment testsKamil Rakoczy2020-06-242-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
| * | | | | | Add plus-assignment operatorKamil Rakoczy2020-06-242-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
| * | | | | | Add or-assignment operatorKamil Rakoczy2020-06-242-1/+11
| | |/ / / / | |/| | | | | | | | | | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* | | | | | Merge pull request #2189 from antmicro/optional-labelswhitequark2020-06-261-2/+2
|\ \ \ \ \ \ | | | | | | | | | | | | | | Add support for optional labels
| * | | | | | Support optional labels at the end of package definitionLukasz Dalek2020-06-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
| * | | | | | Support optional labels at the end of module definitionLukasz Dalek2020-06-241-1/+1
| |/ / / / / | | | | | | | | | | | | | | | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
* | | | | | Merge pull request #2168 from whitequark/assert-unused-exprsclairexen2020-06-2513-43/+46
|\ \ \ \ \ \ | | | | | | | | | | | | | | Use (and ignore) the expression provided to log_assert in NDEBUG builds
| * | | | | | Use [[maybe_unused]] instead of YS_ATTRIBUTE(unused).whitequark2020-06-192-10/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [[maybe_unused]] is available since C++17, so this commit adds a polyfill YS_MAYBE_UNUSED. Once we require C++17 we can drop it.
| * | | | | | Remove YS_ATTRIBUTE(unused) where present just for log_assert()/log_debug().whitequark2020-06-199-26/+26
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