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* | Added "yosys -A"Clifford Wolf2014-07-311-1/+10
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* | Added "yosys -Q"Clifford Wolf2014-07-311-26/+35
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* | Added techmap CONSTMAP featureClifford Wolf2014-07-303-12/+126
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* | Fixed counting verilog line numbers for "// synopsys translate_off" sectionsClifford Wolf2014-07-302-4/+4
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* | Added write_file commandClifford Wolf2014-07-304-5/+84
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* | Added "make -j{N}" support to "make test"Clifford Wolf2014-07-307-22/+39
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* | Improvements in test_cellClifford Wolf2014-07-301-35/+89
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* | New techmap default rules for $shr $sshr $shl $sshlClifford Wolf2014-07-301-282/+62
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* | Using native ezSAT shift ops in satgen, fixed $shift and $shiftx SAT modelsClifford Wolf2014-07-301-36/+39
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* | Added native support for shift operations to ezSATClifford Wolf2014-07-302-1/+95
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* | Added "log_dump_val_worker(char *v)"Clifford Wolf2014-07-301-0/+1
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* | Added CodingStyle documentClifford Wolf2014-07-301-0/+43
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* | Added "kernel/yosys.h" and "kernel/yosys.cc"Clifford Wolf2014-07-308-61/+133
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* | Added "test_cell" commandClifford Wolf2014-07-293-1/+186
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* | Renamed "write_autotest" to "test_autotb" and moved to passes/tests/Clifford Wolf2014-07-295-10/+12
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* | Fixed Verilog pre-processor for files with no trailing newlineClifford Wolf2014-07-291-1/+1
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* | Bugfix in simlib.v for iverilogClifford Wolf2014-07-291-5/+6
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* | Allow "hierarchy -generate" for $__ cellsClifford Wolf2014-07-291-1/+3
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* | Added "techmap -map %{design-name}"Clifford Wolf2014-07-294-10/+29
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* | Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-2912-40/+214
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* | Removed left over debug codeClifford Wolf2014-07-282-2/+0
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* | Fixed part selects of parametersClifford Wolf2014-07-282-7/+31
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* | Set results of out-of-bounds static bit/part select to undefClifford Wolf2014-07-281-5/+31
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* | Fixed RTLIL code generator for part select of parameterClifford Wolf2014-07-281-2/+2
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* | Fixed width detection for part selectsClifford Wolf2014-07-281-2/+2
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* | Added support for "upto" wires to Verilog front- and back-endClifford Wolf2014-07-286-22/+96
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* | Added wire->upto flag for signals such as "wire [0:7] x;"Clifford Wolf2014-07-286-2/+13
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* | Using log_assert() instead of assert()Clifford Wolf2014-07-2852-251/+236
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* | Added std::initializer_list<> constructor to SigSpecClifford Wolf2014-07-282-0/+15
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* | Added cover() to all SigSpec constructorsClifford Wolf2014-07-281-0/+22
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* | Fixed signdness detection of expressions with bit- and part-selectsClifford Wolf2014-07-281-0/+1
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* | Improvements in tests/vloghtbClifford Wolf2014-07-282-11/+17
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* | Added techmap -externClifford Wolf2014-07-273-17/+92
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* | Added proper Design->addModule interfaceClifford Wolf2014-07-273-4/+43
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* | Added topological sorting to techmapClifford Wolf2014-07-272-21/+54
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* | Added SigPool::check(bit)Clifford Wolf2014-07-272-2/+7
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* | Small improvements in PerformanceTimer APIClifford Wolf2014-07-271-6/+7
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* | Fixed bug in opt_cleanClifford Wolf2014-07-271-1/+1
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* | Improved performance of opt_const on large modulesClifford Wolf2014-07-272-29/+157
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* | Added RTLIL::SigSpec::remove_const() handling of packed SigSpecsClifford Wolf2014-07-271-9/+26
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* | Added RTLIL::SigSpecConstIteratorClifford Wolf2014-07-271-0/+18
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* | Fixed a bug in opt_clean and some RTLIL API usage cleanupsClifford Wolf2014-07-272-13/+14
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* | Added log_cmd_error_expectionClifford Wolf2014-07-274-8/+7
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* | Fixed verific bindings for new RTLIL apiClifford Wolf2014-07-272-55/+42
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* | Fixed ilang parser for new RTLIL APIClifford Wolf2014-07-271-10/+10
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* | Using new obj iterator API in a few placesClifford Wolf2014-07-2710-87/+85
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* | Added RTLIL::Module::wire(id) and cell(id) lookup functionsClifford Wolf2014-07-272-2/+20
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* | Added RTLIL::Design::modules()Clifford Wolf2014-07-271-0/+3
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* | Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-2773-223/+223
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* | Added conversion from ObjRange to std::vector and std::setClifford Wolf2014-07-271-0/+15
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