| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Change smtbmc "Warmup failed" status to "PREUNSAT" | Clifford Wolf | 2019-10-03 | 1 | -14/+14 |
| * | Update ABC to git rev 623b5e8 | Clifford Wolf | 2019-10-03 | 1 | -1/+1 |
| * | Bump version | Clifford Wolf | 2019-10-03 | 1 | -1/+1 |
| * | Merge pull request #1419 from YosysHQ/eddie/lazy_derive | Clifford Wolf | 2019-10-03 | 2 | -35/+59 |
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| | * | Fix for svinterfaces | Eddie Hung | 2019-09-30 | 1 | -2/+8 |
| | * | module->derive() to be lazy and not touch ast if already derived | Eddie Hung | 2019-09-30 | 2 | -33/+51 |
| * | | Merge pull request #1422 from YosysHQ/eddie/aigmap_select | Clifford Wolf | 2019-10-03 | 2 | -6/+50 |
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| | * | | Add quick test | Eddie Hung | 2019-09-30 | 1 | -0/+10 |
| | * | | Add -select option to aigmap | Eddie Hung | 2019-09-30 | 1 | -6/+40 |
| * | | | Merge pull request #1429 from YosysHQ/clifford/checkmapped | Clifford Wolf | 2019-10-03 | 2 | -27/+56 |
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| | * | | | Add "check -allow-tbuf" | Clifford Wolf | 2019-10-03 | 1 | -8/+22 |
| | * | | | Add "check -mapped" | Clifford Wolf | 2019-10-02 | 2 | -21/+36 |
| * | | | | Merge pull request #1425 from YosysHQ/dave/ecp5_pdp16 | David Shah | 2019-10-03 | 6 | -2/+184 |
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| | * | | | | ecp5: Fix shuffle_enable port | David Shah | 2019-10-01 | 1 | -2/+2 |
| | * | | | | ecp5: Add support for mapping 36-bit wide PDP BRAMs | David Shah | 2019-10-01 | 6 | -1/+183 |
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| * | | | | Merge pull request #1423 from YosysHQ/eddie/techmap_replace_wire | Eddie Hung | 2019-10-02 | 2 | -0/+32 |
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| | * | | | | Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolf | Eddie Hung | 2019-10-02 | 1 | -4/+8 |
| | * | | | | Extend test with renaming cells with prefix too | Eddie Hung | 2019-10-02 | 1 | -0/+2 |
| | * | | | | Add test | Eddie Hung | 2019-09-30 | 1 | -0/+16 |
| | * | | | | techmap wires named _TECHMAP_REPLACE_.<identifier> to create alias | Eddie Hung | 2019-09-30 | 1 | -0/+10 |
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| * | | | | log_dump() to support State enum | Eddie Hung | 2019-10-02 | 3 | -0/+6 |
| * | | | | Merge pull request #1428 from YosysHQ/clifford/fixbtor | Clifford Wolf | 2019-10-02 | 1 | -6/+9 |
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| | * | | | Fix btor back-end to use "state" instead of "input" for undef init bits | Clifford Wolf | 2019-10-02 | 1 | -6/+9 |
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| * | | | Merge pull request #1426 from YosysHQ/mmicko/fix_environ | Miodrag Milanović | 2019-10-01 | 1 | -0/+2 |
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| | * | | Define environ, fixes #1424 | Miodrag Milanovic | 2019-10-01 | 1 | -0/+2 |
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| * / | Fix typo | Eddie Hung | 2019-09-30 | 1 | -1/+1 |
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| * | Update doc for equiv_opt | Eddie Hung | 2019-09-30 | 1 | -2/+3 |
| * | Merge pull request #1406 from whitequark/connect_rpc | whitequark | 2019-09-30 | 11 | -0/+1767 |
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| | * | rpc: new frontend. | whitequark | 2019-09-30 | 9 | -0/+744 |
| | * | libs: import json11. | whitequark | 2019-09-30 | 3 | -0/+1023 |
| * | | Merge pull request #1397 from btut/fix/python_wrappers_inline_constructors | Eddie Hung | 2019-09-30 | 1 | -0/+2 |
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| | * | | Generate Python wrappers for inline constructors | Benedikt Tutzer | 2019-09-23 | 1 | -0/+2 |
| * | | | Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_in | Miodrag Milanović | 2019-09-30 | 4 | -6/+10 |
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| | * | | | Fix reading aig files on windows | Miodrag Milanovic | 2019-09-29 | 1 | -1/+5 |
| | * | | | Open aig frontend as binary file | Miodrag Milanovic | 2019-09-29 | 4 | -5/+5 |
| * | | | | Bump version | Clifford Wolf | 2019-09-30 | 1 | -1/+1 |
| * | | | | Merge pull request #1412 from YosysHQ/eddie/equiv_opt_async2sync | Clifford Wolf | 2019-09-30 | 1 | -0/+2 |
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| | * | | | | equiv_opt to call async2sync when not -multiclock like SymbiYosys | Eddie Hung | 2019-09-27 | 1 | -0/+2 |
| * | | | | | Merge pull request #1417 from YosysHQ/clifford/fixasync2sync | Clifford Wolf | 2019-09-30 | 1 | -0/+1 |
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| | * | | | | | Fix $dlatch handling in async2sync | Clifford Wolf | 2019-09-30 | 1 | -0/+1 |
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| * | | | | | Add latch test modified from #1363 | Eddie Hung | 2019-09-30 | 2 | -0/+73 |
| * | | | | | Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py} | Eddie Hung | 2019-09-30 | 6 | -122/+46 |
| * | | | | | synth_xilinx: Support latches, remove used-up FF init values. | Marcin Kościelnicki | 2019-09-30 | 3 | -2/+77 |
| * | | | | | Merge pull request #1414 from hzeller/improve-replace-with-empty-map | Eddie Hung | 2019-09-29 | 1 | -0/+2 |
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| | * | | | | | Avoid work in replace() if rules empty. | Henner Zeller | 2019-09-29 | 1 | -0/+2 |
| * | | | | | | Merge pull request #1359 from YosysHQ/xc7dsp | Eddie Hung | 2019-09-29 | 44 | -281/+6234 |
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| | * | | | | | Re-order | Eddie Hung | 2019-09-27 | 2 | -2/+2 |
| | * | | | | | Missing (* mul2dsp *) for sliceB | Eddie Hung | 2019-09-27 | 1 | -2/+2 |
| | * | | | | | Ooops AREG and BREG to default to -1 | Eddie Hung | 2019-09-27 | 1 | -2/+2 |
| | * | | | | | Update doc with max cascade chain of 20 | Eddie Hung | 2019-09-26 | 1 | -2/+4 |
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