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| * | | | | Fix begin/end in generatedalance2020-11-112-7/+4
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* | | | | | Bump versionYosys Bot2021-01-311-1/+1
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* | | | | | Require latest Verific buildMiodrag Milanovic2021-01-301-1/+1
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* | | | | | Bump versionYosys Bot2021-01-301-1/+1
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* | | | | | ast: fix dump_vlog display of casex/casezMarcelina Kościelnicka2021-01-291-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The first child of AST_CASE is the case expression, it's subsequent childrean that are AST_COND* and can be used to discriminate the type of the case.
* | | | | | Merge pull request #2564 from whitequark/flatten-improve-errorwhitequark2021-01-291-1/+1
|\ \ \ \ \ \ | | | | | | | | | | | | | | flatten: clarify confusing error message
| * | | | | | flatten: clarify confusing error message.whitequark2021-01-261-1/+1
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* | | | | | | Bump versionYosys Bot2021-01-291-1/+1
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* | | | | | | Merge pull request #2569 from zachjs/macro-arg-surrounding-spaceswhitequark2021-01-282-1/+25
|\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | verilog: strip leading and trailing spaces in macro args
| * | | | | | | verilog: strip leading and trailing spaces in macro argsZachary Snow2021-01-282-1/+25
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* | | | | | | Merge pull request #2535 from Ravenslofty/scc-specifyClaire Xen2021-01-282-18/+61
|\ \ \ \ \ \ \ | |/ / / / / / |/| | | | | | scc: Add -specify option to find loops in boxes
| * | | | | | scc: Add -specify option to find loops in boxesDan Ravensloft2021-01-262-18/+61
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* | | | | | | Bump versionYosys Bot2021-01-271-1/+1
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* | | | | | | xilinx_dffopt: Don't crash on missing IS_*_INVERTED.Marcelina Kościelnicka2021-01-273-4/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The presence of IS_*_INVERTED on FD* cells follows Vivado, which apparently has been decided by a dice roll. Just assume false if the parameter doesn't exist. Fixes #2559.
* | | | | | | xilinx: Add FDRSE_1, FDCPE_1.Marcelina Kościelnicka2021-01-271-0/+80
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* | | | | | | Merge pull request #2563 from whitequark/cxxrtl-msvcwhitequark2021-01-262-10/+10
|\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | cxxrtl: do not use `->template` for non-dependent names
| * | | | | | | cxxrtl: do not use `->template` for non-dependent names.whitequark2021-01-262-10/+10
| | |/ / / / / | |/| | | | | | | | | | | | | | | | | | | This breaks build on MSVC but not GCC/Clang.
* | | | | | | Merge pull request #2544 from modwizcode/fix-clockwhitequark2021-01-261-7/+15
|\ \ \ \ \ \ \ | |/ / / / / / |/| | | | | | CXXRTL: Fix sliced bits as clock inputs
| * | | | | | Improves the previous commit with a more complete coverage of the casesIris Johnson2021-01-151-12/+12
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| * | | | | | Handle sliced bits as clock inputs (fixes #2542)Iris Johnson2021-01-141-3/+11
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* | | | | | | Bump versionYosys Bot2021-01-261-1/+1
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* | | | | | | Merge pull request #2549 from pgadfort/support-multiple-libswhitequark2021-01-251-15/+21
|\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | adding support for passing multiple liberty files to abc
| * | | | | | | adding support for passing multiple liberty files to abcPeter Gadfort2021-01-181-15/+21
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* | | | | | | | Merge pull request #2550 from zachjs/macro-arg-spaceswhitequark2021-01-252-1/+28
|\ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | verilog: allow spaces in macro arguments
| * | | | | | | | verilog: allow spaces in macro argumentsZachary Snow2021-01-202-1/+28
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* | | | | | | | Bump versionYosys Bot2021-01-251-1/+1
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* | | | | | | | Merge pull request #2558 from YosysHQ/dave/chandle-dpiClaire Xen2021-01-241-1/+16
|\ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | dpi: Support for chandle type
| * | | | | | | | dpi: Support for chandle typeDavid Shah2021-01-231-1/+16
|/ / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | / / Bump versionYosys Bot2021-01-221-1/+1
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* | | | | | | Merge pull request #2553 from zachjs/rand-const-modifiersMiodrag Milanović2021-01-213-2/+19
|\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | Allow combination of rand and const modifiers
| * | | | | | | Allow combination of rand and const modifiersZachary Snow2021-01-213-2/+19
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* | | | | | | Bump versionYosys Bot2021-01-211-1/+1
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* | | | | | | Merge pull request #2552 from YosysHQ/claire/yosyshqClaire Xen2021-01-211-18/+18
|\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | Switch verific bindings from Symbiotic EDA flavored Verific to YosysHQ flavored Verific
| * | | | | | | Switch verific bindings from Symbiotic EDA flavored Verific to YosysHQ ↵Claire Xenia Wolf2021-01-201-18/+18
|/ / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | flavored Verific Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | | | | | | Merge pull request #2536 from TobiasFaller/masterMiodrag Milanović2021-01-201-0/+1
|\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | Fixed missing goto statement in passes/techmap/abc.cc
| * | | | | | | Fixed missing goto statement in passes/techmap/abc.ccTobias Faller2021-01-121-0/+1
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* | | | | | | Merge pull request #2551 from zachjs/wire-logicMiodrag Milanović2021-01-203-9/+65
|\ \ \ \ \ \ \ | |_|/ / / / / |/| | | | | | sv: fix support wire and var data type modifiers
| * | | | | | sv: fix support wire and var data type modifiersZachary Snow2021-01-203-9/+65
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* | | | | | Bump versionYosys Bot2021-01-191-1/+1
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* | | | | | Merge pull request #2547 from zachjs/plugin-so-dsymwhitequark2021-01-181-0/+1
|\ \ \ \ \ \ | | | | | | | | | | | | | | Add plugin.so.dSYM to .gitignore
| * | | | | | Add plugin.so.dSYM to .gitignoreZachary Snow2021-01-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This artifact is automatically generated by the builtin clang on macOS when -g is used.
* | | | | | | Merge pull request #2312 from antmicro/typedef-inoutwhitequark2021-01-184-30/+152
|\ \ \ \ \ \ \ | |/ / / / / / |/| | | | | | Add support for user types in IOs
| * | | | | | Add typedef input/output testKamil Rakoczy2021-01-182-0/+117
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
| * | | | | | Fix input/output attributes when resolving typedef of wireKamil Rakoczy2021-01-181-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
| * | | | | | Parse package user type in module port listLukasz Dalek2021-01-181-30/+32
|/ / / / / / | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com> Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* | / / / / Bump versionYosys Bot2021-01-151-1/+1
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* | | | | opt_share: Fix X and CO signal width for shifted $alu in opt_share.Marcelina Kościelnicka2021-01-142-2/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These need to be the same length as actual Y, not visible part of Y. Fixes #2538.
* | | | | Bump versionYosys Bot2021-01-141-1/+1
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* | | | | Merge pull request #2537 from pepijndevos/spiceClaire Xen2021-01-131-7/+15
|\ \ \ \ \ | |/ / / / |/| | | | Add buffer option to spice backend
| * | | | add buffer option to spice backendPepijn de Vos2021-01-131-7/+15
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