| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add generic __builtin_bswap32 function | Eddie Hung | 2019-06-28 | 1 | -0/+15 |
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| * | Also fix write_aiger for UB | Eddie Hung | 2019-06-28 | 1 | -26/+26 |
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| * | Fix more potential for undefined behaviour due to container invalidation | Eddie Hung | 2019-06-28 | 1 | -6/+10 |
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| * | Update synth_ice40 -device doc to be relevant for -abc9 only | Eddie Hung | 2019-06-28 | 1 | -2/+2 |
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| * | Disable boxing of ECP5 dist RAM due to regression | Eddie Hung | 2019-06-28 | 1 | -1/+1 |
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| * | Add write address to abc_scc_break of ECP5 dist RAM | Eddie Hung | 2019-06-28 | 1 | -1/+1 |
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| * | Fix DO4 typo | Eddie Hung | 2019-06-28 | 1 | -1/+1 |
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| * | Reduce diff with upstream | Eddie Hung | 2019-06-27 | 1 | -4/+2 |
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| * | Extraneous newline | Eddie Hung | 2019-06-27 | 1 | -1/+0 |
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| * | Remove noise from ice40/cells_sim.v | Eddie Hung | 2019-06-27 | 1 | -5/+0 |
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| * | Refactor for one "abc_carry" attribute on module | Eddie Hung | 2019-06-27 | 5 | -82/+84 |
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| * | Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig | Eddie Hung | 2019-06-27 | 2 | -0/+19 |
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| | * | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-27 | 2 | -0/+19 |
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| | | * | Merge pull request #1139 from YosysHQ/dave/check-sim-iverilog | Eddie Hung | 2019-06-27 | 2 | -0/+19 |
| | | |\ | | | | | | | | | tests: Check that Icarus can parse arch sim models | ||||
| | | | * | Add simcells.v, simlib.v, and some output | Eddie Hung | 2019-06-27 | 1 | -1/+11 |
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| | | | * | tests: Check that Icarus can parse arch sim models | David Shah | 2019-06-26 | 2 | -0/+9 |
| | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | | | | Do not use Module::remove() iterator version | Eddie Hung | 2019-06-27 | 1 | -5/+6 |
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| * | | | | Remove redundant doc | Eddie Hung | 2019-06-27 | 1 | -3/+0 |
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| * | | | | Remove &retime when abc9 -fast | Eddie Hung | 2019-06-27 | 1 | -1/+1 |
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| * | | | | Cleanup abc9.cc | Eddie Hung | 2019-06-27 | 1 | -15/+17 |
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| * | | | | Undo iterator based Module::remove() for cells, as containers will not | Eddie Hung | 2019-06-27 | 2 | -11/+2 |
| |/ / / | | | | | | | | | | invalidate | ||||
| * | | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-27 | 4 | -9/+39 |
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| | * | | Grr | Eddie Hung | 2019-06-27 | 1 | -1/+1 |
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| | * | | Capitalisation | Eddie Hung | 2019-06-27 | 1 | -1/+1 |
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| | * | | Make CHANGELOG clearer | Eddie Hung | 2019-06-27 | 1 | -0/+1 |
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| | * | | Merge pull request #1143 from YosysHQ/clifford/fix1135 | Eddie Hung | 2019-06-27 | 4 | -8/+38 |
| | |\ \ | | | | | | | | | Add "pmux2shiftx -norange" | ||||
| | | * | | Add #1135 testcase | Eddie Hung | 2019-06-27 | 2 | -5/+26 |
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| | | * | | Add "pmux2shiftx -norange", fixes #1135 | Clifford Wolf | 2019-06-27 | 2 | -3/+12 |
| | | |/ | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-27 | 0 | -0/+0 |
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| | * | | synth_xilinx -arch -> -family, consistent with older synth_intel | Eddie Hung | 2019-06-27 | 1 | -7/+8 |
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| | * | | Merge pull request #1142 from YosysHQ/clifford/fix1132 | Eddie Hung | 2019-06-27 | 2 | -6/+345 |
| | |\ \ | | | | | | | | | Fix handling of partial covers in muxcover | ||||
| | | * | | Copy tests from eddie/fix1132 | Eddie Hung | 2019-06-27 | 1 | -0/+320 |
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| | | * | | Fix handling of partial covers in muxcover, fixes #1132 | Clifford Wolf | 2019-06-27 | 1 | -6/+25 |
| | | |/ | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | Merge pull request #1138 from YosysHQ/koriakin/xc7nocarrymux | Eddie Hung | 2019-06-27 | 2 | -12/+34 |
| | |\ \ | | |/ | |/| | synth_xilinx: Add -nocarry and -nowidelut options | ||||
| | * | | Merge pull request #1137 from mmicko/cell_sim_fix | Clifford Wolf | 2019-06-26 | 2 | -14/+1 |
| | |\ \ | | | | | | | | | Simulation model verilog fix | ||||
| | | * | | Simulation model verilog fix | Miodrag Milanovic | 2019-06-26 | 2 | -14/+1 |
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| | * | | Improve opt_clean handling of unused public wires | Clifford Wolf | 2019-06-26 | 1 | -2/+2 |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | Improve BTOR2 handling of undriven wires | Clifford Wolf | 2019-06-26 | 1 | -3/+27 |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | Fix segfault on failed VERILOG_FRONTEND::const2ast, closes #1131 | Clifford Wolf | 2019-06-26 | 1 | -1/+1 |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | Do not clean up buffer cells with "keep" attribute, closes #1128 | Clifford Wolf | 2019-06-26 | 1 | -1/+1 |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | Escape scope names starting with dollar sign in smtio.py | Clifford Wolf | 2019-06-26 | 1 | -1/+4 |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | Add more ECP5 Diamond flip-flops. | whitequark | 2019-06-26 | 2 | -30/+91 |
| | | | | | | | | | | | | | | | | This includes all I/O registers, and a few more regular FFs where it was convenient. | ||||
| * | | | Add warning if synth_xilinx -abc9 with family != xc7 | Eddie Hung | 2019-06-27 | 1 | -0/+2 |
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| * | | | Remove unneeded include | Eddie Hung | 2019-06-27 | 1 | -3/+0 |
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| * | | | Merge origin/master | Eddie Hung | 2019-06-27 | 10 | -65/+480 |
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| * | | | Fix spacing | Eddie Hung | 2019-06-26 | 1 | -38/+38 |
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| * | | | Improve debugging message for comb loops | Eddie Hung | 2019-06-26 | 1 | -4/+6 |
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| * | | | Add WE to ECP5 dist RAM's abc_scc_break too | Eddie Hung | 2019-06-26 | 1 | -1/+1 |
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| * | | | Update comment on boxes | Eddie Hung | 2019-06-26 | 2 | -4/+6 |
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| * | | | Add "WE" to dist RAM's abc_scc_break | Eddie Hung | 2019-06-26 | 1 | -3/+3 |
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index : iCE40/yosys | |
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