| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Merge remote-tracking branch 'origin/master' into ice40dsp | Eddie Hung | 2019-07-18 | 28 | -195/+387 |
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| | * | Merge pull request #1184 from whitequark/synth-better-labels | Clifford Wolf | 2019-07-18 | 5 | -17/+21 |
| | |\ | | | | | | | synth_{ice40,ecp5}: more sensible pass label naming | ||||
| | | * | synth_ecp5: rename dram to lutram everywhere. | whitequark | 2019-07-16 | 4 | -13/+13 |
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| | | * | synth_{ice40,ecp5}: more sensible pass label naming. | whitequark | 2019-07-16 | 2 | -5/+9 |
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| | * | | Merge pull request #1203 from whitequark/write_verilog-zero-width-values | Clifford Wolf | 2019-07-18 | 1 | -1/+2 |
| | |\ \ | | | | | | | | | write_verilog: dump zero width constants correctly | ||||
| | | * | | write_verilog: dump zero width constants correctly. | whitequark | 2019-07-16 | 1 | -1/+2 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, zero width constants were dumped as "" (empty string). Unfortunately, 1364-2005 5.2.3.3 indicates that an empty string is equivalent to "\0", and is 8 bits wide, so that's wrong. After this commit, a replication operation with a count of zero is used instead, which is explicitly permitted per 1364-2005 5.1.14, and is defined to have size zero. (Its operand has to have a non-zero size for it to be legal, though.) Fixes #948 (again). | ||||
| | * | | | Remove old $pmux_safe code from write_verilog | Clifford Wolf | 2019-07-17 | 1 | -5/+4 |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | | Merge pull request #1204 from smunaut/fix_1187 | David Shah | 2019-07-17 | 2 | -4/+4 |
| | |\ \ \ | | |/ / | |/| | | ice40: Adapt the relut process passes to the new $lut/SB_LUT4 port map | ||||
| | | * | | ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port map | Sylvain Munaut | 2019-07-16 | 2 | -4/+4 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new mapping introduced in 437fec0d88b4a2ad172edf0d1a861a38845f3b1d needed matching adaptation when converting and optimizing LUTs during the relut process Fixes #1187 (Diagnosis of the issue by @daveshah1 on IRC) Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
| | * | | | Merge pull request #1202 from YosysHQ/cmp2lut_lut6 | Eddie Hung | 2019-07-16 | 4 | -24/+37 |
| | |\ \ \ | | |/ / | |/| | | cmp2lut transformation to support >32 bit LUT masks | ||||
| | | * | | gen_lut to return correctly sized LUT mask | Eddie Hung | 2019-07-16 | 1 | -1/+1 |
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| | | * | | Forgot to commit | Eddie Hung | 2019-07-16 | 1 | -0/+7 |
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| | | * | | Add tests for cmp2lut on LUT6 | Eddie Hung | 2019-07-16 | 2 | -23/+29 |
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| | * | | Merge pull request #1188 from YosysHQ/eddie/abc9_push_inverters | Eddie Hung | 2019-07-16 | 2 | -45/+128 |
| | |\ \ | | | | | | | | | abc9: push inverters driving box inputs (comb outputs) through $lut soft logic | ||||
| | | * | | Add comment | Eddie Hung | 2019-07-13 | 1 | -0/+5 |
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| | | * | | Update test with more accurate LUT mask | Eddie Hung | 2019-07-12 | 1 | -1/+1 |
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| | | * | | duplicate -> clone | Eddie Hung | 2019-07-12 | 1 | -3/+3 |
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| | | * | | More cleanup | Eddie Hung | 2019-07-12 | 1 | -8/+2 |
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| | | * | | Cleanup | Eddie Hung | 2019-07-12 | 1 | -29/+51 |
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| | | * | | Cleanup | Eddie Hung | 2019-07-12 | 1 | -10/+4 |
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| | | * | | Cleanup | Eddie Hung | 2019-07-12 | 1 | -15/+24 |
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| | | * | | More cleanup | Eddie Hung | 2019-07-12 | 1 | -11/+10 |
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| | | * | | Cleanup | Eddie Hung | 2019-07-12 | 1 | -46/+16 |
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| | | * | | Cleanup | Eddie Hung | 2019-07-12 | 1 | -7/+1 |
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| | | * | | Cleanup | Eddie Hung | 2019-07-12 | 1 | -13/+109 |
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| | * | | Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix | Eddie Hung | 2019-07-16 | 9 | -31/+122 |
| | |\ \ | | | | | | | | | abc9/ice40: encapsulate SB_CARRY+SB_LUT4 into one box | ||||
| | | * | | $__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark | Eddie Hung | 2019-07-15 | 7 | -8/+8 |
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| | | * | | ice40_opt to $__ICE40_CARRY_LUT4 into $lut not SB_LUT | Eddie Hung | 2019-07-13 | 1 | -9/+7 |
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| | | * | | Do not double count cells in abc | Eddie Hung | 2019-07-12 | 1 | -2/+2 |
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| | | * | | Use Const::from_string() not its constructor... | Eddie Hung | 2019-07-12 | 1 | -1/+1 |
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| | | * | | Off by one | Eddie Hung | 2019-07-12 | 1 | -1/+1 |
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| | | * | | Fix spacing | Eddie Hung | 2019-07-12 | 1 | -1/+1 |
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| | | * | | Remove double push | Eddie Hung | 2019-07-12 | 1 | -1/+0 |
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| | | * | | Map to and from this box if -abc9 | Eddie Hung | 2019-07-12 | 1 | -2/+3 |
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| | | * | | ice40_opt to handle this box and opt back to SB_LUT4 | Eddie Hung | 2019-07-12 | 1 | -0/+48 |
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| | | * | | Add new box to cells_sim.v | Eddie Hung | 2019-07-12 | 1 | -2/+25 |
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| | | * | | _ABC macro will map and unmap to this new box | Eddie Hung | 2019-07-12 | 2 | -0/+34 |
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| | | * | | Combine SB_CARRY+SB_LUT into one $__ICE40_CARRY_LUT4 box | Eddie Hung | 2019-07-12 | 3 | -25/+13 |
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| | * | | | Merge pull request #1200 from mmicko/fix_typo_liberty_cc | Clifford Wolf | 2019-07-16 | 1 | -1/+1 |
| | |\ \ \ | | | | | | | | | | | Fix typo, double "of" | ||||
| | | * | | | Fix typo, double "of" | Miodrag Milanovic | 2019-07-16 | 1 | -1/+1 |
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| | * | | | | Merge pull request #1199 from mmicko/extract_fa_fix | Clifford Wolf | 2019-07-16 | 1 | -2/+2 |
| | |\ \ \ \ | | |/ / / | |/| | | | Fix check logic in extract_fa | ||||
| | | * | | | Fix check logic in extract_fa | Miodrag Milanovic | 2019-07-16 | 1 | -2/+2 |
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| | * | | | Merge pull request #1196 from YosysHQ/eddie/fix1178 | Eddie Hung | 2019-07-15 | 1 | -5/+12 |
| | |\ \ \ | | | | | | | | | | | Fix different synth results between with and without debug output "-g" | ||||
| | | * | | | Revert "Add log_checkpoint function and use it in opt_muxtree" | Eddie Hung | 2019-07-15 | 3 | -9/+0 |
| | | | | | | | | | | | | | | | | | | | | | This reverts commit 0e6c83027f24cdf7082606a5631468ad28f41574. | ||||
| | | * | | | Revert "Fix first divergence in #1178" | Eddie Hung | 2019-07-15 | 1 | -5/+1 |
| | | | | | | | | | | | | | | | | | | | | | This reverts commit 1122a2e0671ed00b7c03658f5012e34df12f26de. | ||||
| | | * | | | Merge branch 'master' into eddie/fix1178 | Eddie Hung | 2019-07-15 | 26 | -93/+1204 |
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| | | * | | | | Redesign log_id_cache so that it doesn't keep IdString instances referenced, ↵ | Clifford Wolf | 2019-07-15 | 1 | -6/+13 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fixes #1178 Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | | * | | | | Add log_checkpoint function and use it in opt_muxtree | Clifford Wolf | 2019-07-15 | 3 | -0/+9 |
| | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | | * | | | | Fix first divergence in #1178 | Eddie Hung | 2019-07-09 | 1 | -1/+5 |
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| | * | | | | | Merge pull request #1189 from YosysHQ/eddie/fix1151 | Clifford Wolf | 2019-07-15 | 1 | -0/+4 |
| | |\ \ \ \ \ | | | | | | | | | | | | | | | Error out if enable > dbits in memory_bram file | ||||
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index : iCE40/yosys | |
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