| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | | | | | | | | | | write_xaiger: default value for abc9_init | Eddie Hung | 2020-02-13 | 1 | -1/+1 | |
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| | * | | | | | | | | | | abc9: fix abc9_arrival for flops | Eddie Hung | 2020-02-13 | 2 | -4/+36 | |
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| | * | | | | | | | | | | abc9: deprecate abc9_ff.init wire for (* abc9_init *) attr | Eddie Hung | 2020-02-13 | 2 | -24/+14 | |
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| * | | | | | | | | | | Merge pull request #1699 from YosysHQ/eddie/fix_iopad_init | Eddie Hung | 2020-02-13 | 2 | -0/+46 | |
| |\ \ \ \ \ \ \ \ \ \ | |/ / / / / / / / / |/| | | | | | | | | | iopadmap: move \init attributes from outpad output to its input | |||||
| | * | | | | | | | | | Fine tune #1699 tests | Eddie Hung | 2020-02-13 | 1 | -14/+14 | |
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| | * | | | | | | | | | iopadmap: fixes as suggested by @mwkmwkmwk | Eddie Hung | 2020-02-13 | 1 | -19/+11 | |
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| | * | | | | | | | | | iopadmap: move \init attributes from outpad output to its input | Eddie Hung | 2020-02-13 | 2 | -3/+57 | |
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| * | | | | | | | | | Merge pull request #1694 from rqou/json_compat_fix | Claire Wolf | 2020-02-13 | 1 | -3/+3 | |
| |\ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | json: Change compat mode to directly emit ints <= 32 bits | |||||
| | * | | | | | | | | | json: Change compat mode to directly emit ints <= 32 bits | R. Ou | 2020-02-09 | 1 | -3/+3 | |
| | | |_|_|_|_|/ / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This increases compatibility with certain older parsers in some cases that worked before commit 15fae357 but do not work with the current compat-int mode | |||||
| * | | | | | | | | | Merge pull request #1679 from thasti/delay-parsing | N. Engelhardt | 2020-02-13 | 2 | -2/+7 | |
| |\ \ \ \ \ \ \ \ \ | |_|_|/ / / / / / |/| | | | | | | | | Fix crash on wire declaration with delay | |||||
| | * | | | | | | | | add testcase for #1614 | Stefan Biereigel | 2020-02-03 | 1 | -0/+5 | |
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| | * | | | | | | | | correct wire declaration grammar for #1614 | Stefan Biereigel | 2020-02-03 | 1 | -2/+2 | |
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| * | | | | | | | | | abc9: cleanup | Eddie Hung | 2020-02-10 | 2 | -41/+41 | |
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| * | | | | | | | | | Merge pull request #1670 from rodrigomelo9/master | Eddie Hung | 2020-02-10 | 7 | -3/+152 | |
| |\ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | $readmem[hb] file inclusion is now relative to the Verilog file | |||||
| | * | | | | | | | | | Added 'set -e' into tests/memfile/run-test.sh | Rodrigo Alejandro Melo | 2020-02-06 | 1 | -0/+20 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Also added two checks for situations where the execution must fail. Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar> | |||||
| | * | | | | | | | | | Modified $readmem[hb] to use '\' or '/' according the OS | Rodrigo Alejandro Melo | 2020-02-06 | 1 | -1/+6 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar> | |||||
| | * | | | | | | | | | Merge branch 'master' into master | Rodrigo A. Melo | 2020-02-03 | 10 | -4/+367 | |
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| | * \ \ \ \ \ \ \ \ \ | Merge branch 'master' of https://github.com/YosysHQ/yosys | Rodrigo Alejandro Melo | 2020-02-03 | 12 | -112/+369 | |
| | |\ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Solved a conflict into the CHANGELOG Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar> | |||||
| | * | | | | | | | | | | | Replaced strlen by GetSize into simplify.cc | Rodrigo Alejandro Melo | 2020-02-03 | 1 | -2/+2 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As recommended in CodingReadme. Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar> | |||||
| | * | | | | | | | | | | | Removed 'synth' into tests/memfile/run-test.sh | Rodrigo Alejandro Melo | 2020-02-02 | 1 | -8/+8 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com> | |||||
| | * | | | | | | | | | | | Added content1.dat into tests/memfile | Rodrigo Alejandro Melo | 2020-02-02 | 2 | -21/+81 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modified run-test.sh to use it. Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com> | |||||
| | * | | | | | | | | | | | Removed a line jump into the CHANGELOG | Rodrigo Alejandro Melo | 2020-02-01 | 1 | -3/+2 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com> | |||||
| | * | | | | | | | | | | | Added tests/memfile to 'make test' with an extra testcase | Rodrigo Alejandro Melo | 2020-02-01 | 2 | -16/+11 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com> | |||||
| | * | | | | | | | | | | | Added a test for the Memory Content File inclusion using $readmemb | Rodrigo Alejandro Melo | 2020-02-01 | 3 | -0/+63 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com> | |||||
| | * | | | | | | | | | | | Fixed a bug in the new feature of $readmem[hb] when an empty string is provided | Rodrigo Alejandro Melo | 2020-02-01 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com> | |||||
| | * | | | | | | | | | | | Modified the new search for files of $readmem[hb] to be backward compatible | Rodrigo Alejandro Melo | 2020-01-31 | 1 | -3/+7 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com> | |||||
| | * | | | | | | | | | | | $readmem[hb] file inclusion is now relative to the Verilog file | Rodrigo Alejandro Melo | 2020-01-31 | 2 | -2/+4 | |
| | | |_|_|_|_|_|/ / / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com> | |||||
| * | | | | | | | | | | | Merge pull request #1669 from thasti/pyosys-attrs | N. Engelhardt | 2020-02-10 | 1 | -2/+38 | |
| |\ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | Make RTLIL attributes accessible via pyosys | |||||
| | * | | | | | | | | | | | remove namespace mention from inheritance information | Stefan Biereigel | 2020-02-03 | 1 | -1/+1 | |
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| | * | | | | | | | | | | | expose polymorphism through python wrappers | Stefan Biereigel | 2020-02-03 | 1 | -2/+8 | |
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| | * | | | | | | | | | | | add inheritance for pywrap generators | Stefan Biereigel | 2020-01-30 | 1 | -0/+30 | |
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| * | | | | | | | | | | | Merge pull request #1695 from whitequark/manual-explain-wire-upto-offset | whitequark | 2020-02-09 | 1 | -0/+7 | |
| |\ \ \ \ \ \ \ \ \ \ \ | |_|_|_|_|/ / / / / / |/| | | | | | | | | | | manual: explain RTLIL::Wire::{upto,offset} | |||||
| | * | | | | | | | | | | manual: explain RTLIL::Wire::{upto,offset}. | whitequark | 2020-02-09 | 1 | -0/+7 | |
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| * | | | | | | | | | | Remove unnecessary comma | Eddie Hung | 2020-02-07 | 1 | -3/+2 | |
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| * | | | | | | | | | | Merge pull request #1687 from YosysHQ/eddie/fix_ystests | Eddie Hung | 2020-02-07 | 2 | -9/+7 | |
| |\ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | Fix shiftx2mux, fix yosys-tests | |||||
| | * | | | | | | | | | | techmap: fix shiftx2mux decomposition | Eddie Hung | 2020-02-07 | 1 | -8/+6 | |
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| | * | | | | | | | | | | Fix misc.abc9.abc9_abc9_luts | Eddie Hung | 2020-02-07 | 1 | -1/+1 | |
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| * | | | | | | | | | | xilinx: Add support for LUT RAM on LUT4-based devices. | Marcin Kościelnicki | 2020-02-07 | 5 | -27/+42 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are multiple other kinds of RAMs supported on these devices, but RAM16X1D is the only dual-port one. Fixes #1549 | |||||
| * | | | | | | | | | | xilinx: Initial support for LUT4 devices. | Marcin Kościelnicki | 2020-02-07 | 6 | -54/+235 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds support for mapping logic, including LUTs, wide LUTs, and carry chains. Fixes #1547 | |||||
| * | | | | | | | | | | Merge pull request #1685 from dh73/gowin | Eddie Hung | 2020-02-06 | 1 | -1/+1 | |
| |\ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | Removing cells_sim from GoWin bram techmap | |||||
| | * | | | | | | | | | | Removing cells_sim.v from bram techmap pass | Diego H | 2020-02-06 | 1 | -1/+1 | |
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| * | | | | | | | | | | | Merge pull request #1683 from whitequark/write_verilog-memattrs | whitequark | 2020-02-07 | 1 | -0/+1 | |
| |\ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | write_verilog: dump $mem cell attributes | |||||
| | * | | | | | | | | | | | write_verilog: dump $mem cell attributes. | whitequark | 2020-02-06 | 1 | -0/+1 | |
| | | |_|_|_|_|_|_|_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Verilog backend already dumps attributes on RTLIL::Memory objects but not on `$mem` cells. | |||||
| * | | | | | | | | | | | xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*. | Marcin Kościelnicki | 2020-02-07 | 11 | -1/+370 | |
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| * | | | | | | | | | | | xilinx: Add support for Spartan 3A DSP block RAMs. | Marcin Kościelnicki | 2020-02-07 | 3 | -1/+39 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Part of #1550 | |||||
| * | | | | | | | | | | | Merge pull request #1684 from YosysHQ/eddie/xilinx_arith_map | Eddie Hung | 2020-02-06 | 1 | -109/+43 | |
| |\ \ \ \ \ \ \ \ \ \ \ | |_|/ / / / / / / / / |/| | | | | | | | | | | Fix/cleanup +/xilinx/arith_map.v | |||||
| | * | | | | | | | | | | Fix $lcu -> MUXCY mapping, credit @mwkmwkmwk | Eddie Hung | 2020-02-06 | 1 | -4/+5 | |
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| | * | | | | | | | | | | Fix/cleanup +/xilinx/arith_map.v | Eddie Hung | 2020-02-06 | 1 | -111/+44 | |
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| * | | | | | | | | | | edif: more resilience to mismatched port connection sizes. | Marcin Kościelnicki | 2020-02-06 | 1 | -16/+27 | |
| | |/ / / / / / / / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes #1653. | |||||
| * | | | | | | | | | Merge pull request #1682 from YosysHQ/eddie/opt_after_techmap | Eddie Hung | 2020-02-05 | 8 | -5/+9 | |
| |\ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | synth_*: call 'opt -fast' after 'techmap' | |||||
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