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* | Makefile: pass PRETTY=0 to ABCXiretza2021-07-051-1/+1
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* | Makefile: don't bake DESTDIR into libyosys DT_SONAMEXiretza2021-07-051-2/+2
| | | | | | | | | | | | DESTDIR is only used as a temporary destination for installed files before they are packaged into an archive; the "real" installed location is determined by PREFIX/{BIN,LIB,DAT}DIR.
* | Makefile: clean up PYOSYS configurationXiretza2021-07-051-34/+10
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* | Merge pull request #2842 from whitequark/fix-wasi-buildwhitequark2021-06-191-1/+1
|\ \ | | | | | | Fix WASI build after commit 1d88bea1
| * | Fix WASI build after commit 1d88bea1.whitequark2021-06-191-1/+1
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* | Merge pull request #2836 from YosysHQ/gatecat/pyosys-sigintMiodrag Milanović2021-06-181-0/+2
|\ \ | | | | | | pyosys: Clear SIGINT handler after Python loads
| * | pyosys: Clear SIGINT handler after Python loadsgatecat2021-06-161-0/+2
| |/ | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Move interface expansion in hierarchy.cc into a helper classRupert Swarbrick2021-06-161-100/+189
| | | | | | | | | | | | | | | | | | | | | | | | There should be no functional change, but this splits up the control flow across functions, using class fields to hold the state that's being tracked. The result should be a bit easier to read. This is part of work to add bind support, but I'm doing some refactoring in the hierarchy pass to make the code a bit easier to work with. The idea is that (eventually) the IFExpander object will hold all the logic for expanding interfaces, and then other code can do bind insertion.
* | sv: fix up end label checkingZachary Snow2021-06-167-7/+98
| | | | | | | | | | | | | | - disallow [gen]blocks with an end label but not begin label - check validity of module end label - fix memory leak of package name and end label - fix memory leak of module end label
* | Include blif reader header in public facing extension header files.Ashton Snelgrove2021-06-161-0/+1
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* verilog: fix leaking of type names in parserXiretza2021-06-141-0/+2
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* verilog: fix wildcard port connections leaking memoryXiretza2021-06-141-0/+1
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* ast: delete wires and localparams after finishing const evaluationXiretza2021-06-141-0/+8
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* verilog: fix leaking ASTNodesXiretza2021-06-142-7/+15
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* ast: fix error condition causing assert to failXiretza2021-06-141-2/+1
| | | | | type2str returns a string that doesn't start with $ or \, so it can't be assigned to an IdString.
* macos: fix leak in proc_self_dirname()Zachary Snow2021-06-141-1/+3
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* Simplify some RTLIL destructorsRupert Swarbrick2021-06-141-10/+10
| | | | | No change in behaviour, but use range-based for loops instead of iterators.
* verilog: Squash a memory leak.Marcelina Kościelnicka2021-06-144-19/+14
| | | | That was added in ecc22f7fedfa639482dbc55a05709da85116a60f
* Add regression test for #2824.Marcelina Kościelnicka2021-06-111-0/+7
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* opt_muxtree: Update port_off and port_idx even for constant bitsgatecat2021-06-111-17/+16
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* opt_expr: Fix mul/div/mod by POT patterns to support >= 32 bits.Marcelina Kościelnicka2021-06-093-122/+120
| | | | | The previous code, in addition to being needlessly limitted to 32 bits in the first place, also had UB for the 31th bit (doing 1 << 31).
* opt_expr: Optimize div/mod by const 1.Marcelina Kościelnicka2021-06-091-4/+4
| | | | | | | | Turns out the code for div by a power of 2 is already almost capable of optimizing this to a shift-by-0 or and-with-0, which will be further folded into nothingness; let's beef it up to handle div by 1 as well. Fixes #2820.
* Merge pull request #2817 from YosysHQ/claire/fixemailsClaire Xen2021-06-09325-1308/+1311
|\ | | | | Fixing old e-mail addresses and deadnames
| * Fix deadname SVN linksClaire Xenia Wolf2021-06-092-3/+3
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
| * Intersynth URLClaire Xenia Wolf2021-06-092-2/+2
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
| * More deadname stuffClaire Xenia Wolf2021-06-092-4/+4
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
| * Fix icestorm linksClaire Xenia Wolf2021-06-092-516/+516
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
| * More deadname stuffClaire Xenia Wolf2021-06-0910-27/+27
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| * Use HTTPS for website links, gatecat emailClaire Xenia Wolf2021-06-0920-26/+26
| | | | | | | | | | | | | | | | | | | | git ls-tree -r --name-only HEAD | xargs sed -i -rf ~/fixemails.sed s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+(Shah|gatecat)\s+<(dave|david|gatecat)@(symbioticeda.com|yosyshq.com|ds0.me)>/gatecat <gatecat@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/|http://yosyshq.net/yosys/,https://yosyshq.net/yosys/,g;
| * Fix files with CRLF line endingsClaire Xenia Wolf2021-06-095-422/+422
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| * Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-08309-331/+330
| | | | | | | | | | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
| * Add claire deadname stuff to .mailmapClaire Xenia Wolf2021-06-081-0/+4
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | verilog: check for module scope identifiers during width detectionZachary Snow2021-06-084-13/+41
| | | | | | | | | | | | | | | | The recent fix for case expression width detection causes the width of the expressions to be queried before they are simplified. Because the logic supporting module scope identifiers only existed in simplify, looking them up would fail during width detection. This moves the logic to a common helper used in both simplify() and detectSignWidthWorker().
* | mem2reg: tolerate out of bounds constant accessesZachary Snow2021-06-084-5/+94
| | | | | | | | This brings the mem2reg behavior in line with the nomem2reg behavior.
* | autoname: simple perf optimizationsZachary Snow2021-06-081-11/+15
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* sv: support tasks and functions within packagesZachary Snow2021-06-015-2/+56
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* kernel/mem: Recognize some deprecated memory port configs.Marcelina Kościelnicka2021-06-011-0/+10
| | | | | | | | | | Transparency is meaningless for asynchronous ports, so we assume transparent == false to simplify the code in this case. Likewise, enable is meaningless, and we assume it is const-1. However, turns out that nMigen emits the former, and Verilog frontend emits the latter, so squash these issues when ingesting a $memrd cell. Fixes #2811.
* memory_map: Improve start_offset handling.Marcelina Kościelnicka2021-05-312-35/+131
| | | | Fixes #2775.
* memory_share: Add read port merging.Marcelina Kościelnicka2021-05-291-0/+140
| | | | | This is mostly meant for wide port recognition, but may also happen to merge some ports with compatible initial/reset values (eg. 0 vs x).
* memory_share: Improve sat-based port sharing.Marcelina Kościelnicka2021-05-281-117/+151
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* Make a few passes auto-call Mem::narrow instead of rejecting wide ports.Marcelina Kościelnicka2021-05-285-33/+10
| | | | | | This essentially adds wide port support for free in passes that don't have a usefully better way of handling wide ports than just breaking them up to narrow ports, avoiding "please run memory_narrow" annoyance.
* backends/verilog: Add support for memory read port reset and init value.Marcelina Kościelnicka2021-05-271-9/+81
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* backends/verilog: Add wide port support.Marcelina Kościelnicka2021-05-271-43/+88
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* memory_share: Improve same-address merging, recognize wide write ports.Marcelina Kościelnicka2021-05-271-204/+77
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* kernel/mem: Add helpers for write port widening.Marcelina Kościelnicka2021-05-272-0/+57
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* kernel/mem: Add sub_addr helpers.Marcelina Kościelnicka2021-05-263-26/+32
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* kernel/mem: Add prepare_wr_merge helper.Marcelina Kościelnicka2021-05-262-0/+27
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* backends/verilog: Try to preserve mem write port priorities.Marcelina Kościelnicka2021-05-261-32/+84
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* mem/extract_rdff: Fix "no FF made" edge case.Marcelina Kościelnicka2021-05-252-3/+9
| | | | | | | When converting a sync transparent read port with const address to async read port, nothing at all needs to be done other than clk_enable change, and thus we have no FF cell to return. Handle this case correctly in the helper and in its users.
* memory_bram: Reuse extract_rdff helper for make_outreg.Marcelina Kościelnicka2021-05-255-40/+52
| | | | | Also properly skip read ports with init value or reset when not making use of make_outreg. Proper support for matching those will land later.
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-07 20:09:51 +0000