aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* abc9: add flow3mfs scriptLofty2022-02-101-1/+7
|
* Bump versiongithub-actions[bot]2022-01-121-1/+1
|
* Forgot oneMiodrag Milanovic2022-01-111-1/+1
|
* Change url to httpsMiodrag Milanovic2022-01-112-2/+2
|
* Next dev cycleMiodrag Milanovic2022-01-112-2/+5
|
* Release version 0.13Miodrag Milanovic2022-01-112-3/+3
|
* Update CHANGELOGMiodrag Milanovic2022-01-111-6/+19
|
* Bump versiongithub-actions[bot]2022-01-091-1/+1
|
* sv: auto add nosync to certain always_comb local varsZachary Snow2022-01-0710-0/+265
| | | | | If a local variable is always assigned before it is used, then adding nosync prevents latches from being needlessly generated.
* sv: fix size cast internal expression extensionZachary Snow2022-01-074-2/+156
|
* Bump versiongithub-actions[bot]2022-01-051-1/+1
|
* logger: fix unmatched expected warnings and errorsZachary Snow2022-01-042-11/+53
| | | | | | | | - Prevent unmatched expected error patterns from self-matching - Prevent infinite recursion on unmatched expected warnings - Always print the error message for unmatched error patterns - Add test coverage for all unmatched message types - Add test coverage for excess matched logs and warnings
* opt_dff: fix sequence point copy paste bugAustin Seipp2022-01-041-1/+1
| | | | | | | | | | | | | | | | Newer GCCs emit the following warning for opt_dff: passes/opt/opt_dff.cc:560:17: warning: operation on ‘ff.Yosys::FfData::has_clk’ may be undefined [-Wsequence-point] 560 | ff.has_clk = ff.has_ce = ff.has_clk = false; | ~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Which is correct: the order of whether the read or write of has_clk occurs first is undefined since there is no sequence point between them. This is almost certainly just a typo/copy paste error and objectively wrong, so just fix it. Signed-off-by: Austin Seipp <aseipp@pobox.com>
* manual: Fix cell-stmt ordergatecat2022-01-031-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Bump versiongithub-actions[bot]2022-01-041-1/+1
|
* fix iverilog compatibility for new case expr testsZachary Snow2022-01-032-2/+2
|
* fixup verilog doubleslash testZachary Snow2022-01-032-0/+3
| | | | | - add generated doubleslash.v to .gitignore - ensure backend verilog can be read again
* sv: fix size cast clipping expression widthZachary Snow2022-01-033-1/+11
|
* Update manualMiodrag Milanovic2022-01-031-1/+21
|
* Bump versiongithub-actions[bot]2021-12-261-1/+1
|
* Merge pull request #3127 from whitequark/cxxrtl-no-reset-elidedCatherine2021-12-251-0/+2
|\ | | | | cxxrtl: don't reset elided wires with \init attribute
| * cxxrtl: don't reset elided wires with \init attribute.Catherine2021-12-251-0/+2
| |
* | Bump versiongithub-actions[bot]2021-12-221-1/+1
| |
* | intel_alm: disable 256x40 M10K modeLofty2021-12-221-9/+3
| | | | | | | | | | This BRAM mode uses both address ports, making it effectively single-port. Since memory_bram can't presently map to single-port memories, remove it.
* | Bump versiongithub-actions[bot]2021-12-211-1/+1
| |
* | memory_share: Fix SAT-based sharing for wide ports.Marcelina Kościelnicka2021-12-202-1/+37
| | | | | | | | Fixes #3117.
* | Bump versiongithub-actions[bot]2021-12-191-1/+1
| |
* | fix width detection of array querying function in case and case item expressionsZachary Snow2021-12-175-2/+50
| | | | | | | | | | I also removed the unnecessary shadowing of `width_hint` and `sign_hint` in the corresponding case in `simplify()`.
* | Bump versiongithub-actions[bot]2021-12-171-1/+1
|/
* Merge pull request #3115 from whitequark/issue-3112Catherine2021-12-161-3/+4
|\ | | | | cxxrtl: demote wires not inlinable only in debug_eval to locals
| * cxxrtl: demote wires not inlinable only in debug_eval to locals.Catherine2021-12-151-3/+4
| | | | | | | | | | | | Fixes #3112. Co-authored-by: Irides <irides@irides.network>
* | Merge pull request #3114 from whitequark/issue-3113Catherine2021-12-161-1/+1
|\ \ | | | | | | bugpoint: avoid infinite loop between -connections and -wires
| * | bugpoint: avoid infinite loop between -connections and -wires.Catherine2021-12-151-1/+1
| | | | | | | | | | | | Fixes #3113.
* | | preprocessor: do not destroy double slash escaped identifiersThomas Sailer2021-12-152-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The preprocessor currently destroys double slash containing escaped identifiers (for example \a//b ). This is due to next_token trying to convert single line comments (//) into /* */ comments. This then leads to an unintuitive error message like this: ERROR: syntax error, unexpected '*' This patch fixes the error by recognizing escaped identifiers and returning them as single token. It also adds a testcase.
* | | Bump versiongithub-actions[bot]2021-12-151-1/+1
| | |
* | | Merge pull request #3111 from whitequark/issue-3110Catherine2021-12-141-1/+2
|\| | | | | | | | Fix null pointer dereference after failing to extract DFF from memory
| * | Fix null pointer dereference after failing to extract DFF from memory.Catherine2021-12-141-1/+2
| |/ | | | | | | Fixes #3110.
* / Hotfix for run_shell auto-detectionClaire Xenia Wolf2021-12-141-0/+3
|/ | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Bump versiongithub-actions[bot]2021-12-141-1/+1
|
* Merge pull request #3108 from YosysHQ/claire/verificdefsClaire Xen2021-12-131-1/+2
|\ | | | | Add YOSYS to the implicitly defined verilog macros in verific
| * Add YOSYS to the implicitly defined verilog macros in verificClaire Xenia Wolf2021-12-131-1/+2
|/ | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Bump versiongithub-actions[bot]2021-12-131-1/+1
|
* Add clean_zerowidth pass, use it for Verilog output.Marcelina Kościelnicka2021-12-123-1/+214
| | | | | | | This should remove instances of zero-width sigspecs in the netlist, avoiding problems in the Verilog backend with emitting them. See #3103.
* Merge pull request #3105 from whitequark/cxxrtl-reset-memories-2Catherine2021-12-122-108/+80
|\ | | | | cxxrtl: preserve interior memory pointers across reset
| * cxxrtl: preserve interior memory pointers across reset.Catherine2021-12-112-95/+67
| | | | | | | | | | | | | | | | Before this commit, values, wires, and memories with an initializer were value-initialized in emitted C++ code. After this commit, all values, wires, and memories are default-initialized, and the default constructor of generated modules calls the reset() method, which assigns the members that have an initializer.
| * cxxrtl: use unique_ptr<value<>[]> to store memory contents.whitequark2021-12-111-16/+16
| | | | | | | | This makes the depth properly immutable.
* | Bump versiongithub-actions[bot]2021-12-121-1/+1
| |
* | Fix unused param warning with ENABLE_NDEBUG.Marcelina Kościelnicka2021-12-121-1/+1
| |
* | rtlil: Dump empty connections when whole module is selected.Marcelina Kościelnicka2021-12-121-2/+2
| | | | | | | | | | Without this, empty connections will be always skipped by `dump`, since they contain no selected wires. This makes debugging rather confusing.
* | Merge pull request #3103 from whitequark/write_verilog-more-zero-width-valuesCatherine2021-12-111-1/+2
|\ \ | |/ |/| write_verilog: dump zero width sigspecs correctly
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-13 08:01:40 +0000