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* Imporove yosys-smtbmc error handling, Improve VCD outputClifford Wolf2018-03-052-23/+49
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix connwrappers help messageClifford Wolf2018-03-041-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve handling of warning messagesClifford Wolf2018-03-043-12/+42
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Update copyright headerClifford Wolf2018-03-041-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve SMT2 encoding of $reduce_{and,or,bool}Clifford Wolf2018-03-041-1/+9
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix a hangup in yosys-smtbmc error handlingClifford Wolf2018-03-041-3/+5
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add proper SVA seq.triggered supportClifford Wolf2018-03-043-37/+102
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "synth -noshare"Clifford Wolf2018-03-041-2/+11
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add Verific SVA support for "seq and seq" expressionsClifford Wolf2018-03-041-24/+94
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Refactor Verific SVA importer property parserClifford Wolf2018-03-041-56/+82
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add VerificClocking class and refactor Verific DFF handlingClifford Wolf2018-03-043-126/+196
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improved error handling in yosys-smtbmcClifford Wolf2018-03-031-1/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add SVA support for sequence ORClifford Wolf2018-03-031-22/+33
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Terminate running SMT solver when smtbmc is terminatedClifford Wolf2018-03-031-1/+31
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix smtbmc smtc/aiw parser for wire names containing []Clifford Wolf2018-03-031-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix handling of SVA "until seq.triggered" propertiesClifford Wolf2018-03-021-7/+25
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Update SVA cheat sheet in verificsva.ccClifford Wolf2018-03-021-2/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix in Verific SVA importer handling of until_withClifford Wolf2018-03-011-7/+5
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Mangle names with square brackets in VCD files to work around issues in gtkwaveClifford Wolf2018-03-011-2/+8
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fixes and improvements in Verific SVA importerClifford Wolf2018-03-013-83/+136
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add $rose/$fell support to Verific bindingsClifford Wolf2018-03-011-3/+22
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge branch 'verificsva-ng'Clifford Wolf2018-02-284-403/+752
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| * Add support for PRIM_SVA_UNTIL to new SVA importerClifford Wolf2018-02-281-0/+27
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Add DFSM generator to verific SVA importerClifford Wolf2018-02-281-19/+272
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Continue refactoring of Verific SVA importer codeClifford Wolf2018-02-283-671/+172
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Major redesign of Verific SVA importerClifford Wolf2018-02-272-6/+574
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add -lz for verific buildsClifford Wolf2018-02-271-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add handling of verific OPER_REDUCE_NORClifford Wolf2018-02-261-0/+6
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add handling of verific OPER_SELECTOR and OPER_WIDE_SELECTORClifford Wolf2018-02-261-0/+13
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add handling of verific OPER_NTO1MUX and OPER_WIDE_NTO1MUXClifford Wolf2018-02-261-0/+25
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "SVA syntax cheat sheet" comment to verificsva.ccClifford Wolf2018-02-261-0/+34
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add $dlatchsr support to clk2fflogicClifford Wolf2018-02-261-4/+25
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* Small fixes and improvements in $allconst/$allseq handlingClifford Wolf2018-02-262-16/+23
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix opt_rmdff handling of $dlatchsrClifford Wolf2018-02-261-0/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge branch 'forall'Clifford Wolf2018-02-2317-98/+424
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| * Add smtbmc support for exist-forall problemsClifford Wolf2018-02-236-89/+357
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Add $allconst and $allseq cell typesClifford Wolf2018-02-2311-9/+67
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add Verific SVA support for ranges in repetition operatorClifford Wolf2018-02-221-5/+26
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* Add support for SVA throughout via VerificClifford Wolf2018-02-212-3/+7
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* Add support for mockup clock signals in yosys-smtbmc vcd outputClifford Wolf2018-02-203-6/+111
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #507 from cr1901/msys2Clifford Wolf2018-02-191-3/+3
|\ | | | | Improve msys2 flags for building abc.
| * Improve msys2 flags for building abc.William D. Jones2018-02-191-3/+3
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* Add support for SVA sequence concatenation ranges via verificClifford Wolf2018-02-183-16/+144
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add support for SVA until statements via VerificClifford Wolf2018-02-183-34/+138
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Move Verific SVA importer to extra C++ source fileClifford Wolf2018-02-184-1279/+1370
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge Verific SVA preprocessor and SVA importerClifford Wolf2018-02-181-79/+44
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* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2018-02-161-0/+6
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| * Improve handling of "bus" pins in liberty front-end (some files use ↵Clifford Wolf2018-02-151-0/+6
| | | | | | | | | | | | bus.pin.direction) Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Fix verific PRIM_SVA_AT handling in properties with PRIM_SVA_DISABLE_IFFClifford Wolf2018-02-152-1/+35
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* Fixed yosys-config for binary distributions with VerificClifford Wolf2018-02-131-3/+11
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
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