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* Added "aig" passClifford Wolf2015-06-093-16/+291
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* synth_ice40 now flattens by defaultClifford Wolf2015-06-091-4/+8
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* Added cellaigs APIClifford Wolf2015-06-094-2/+173
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* Merge clock inverters in memory_dffClifford Wolf2015-06-091-16/+37
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* Merge branch 'verilog-backend-memV2' of github.com:wluker/yosysClifford Wolf2015-06-091-54/+110
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| * $mem cell in verilog backend : grouped writes by clockluke whittlesey2015-06-082-58/+110
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| * Bug fix in $mem verilog backend + changed tests/bram flow of make test.luke whittlesey2015-06-042-16/+20
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* | Fixed "avail_parameters" handling in module clone/copyClifford Wolf2015-06-081-0/+2
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* | Added log_dump() support for IdStringsClifford Wolf2015-06-082-0/+5
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* | Fixed handling of parameters with reversed rangeClifford Wolf2015-06-081-1/+1
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* Added opt_share -share_allClifford Wolf2015-05-312-16/+32
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* Added iCE40 PLL cellsClifford Wolf2015-05-311-0/+168
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* Added liberty dont_use support to dfflibmapClifford Wolf2015-05-311-0/+4
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* Fixed signedness of genvar expressionsClifford Wolf2015-05-291-2/+2
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* Added output args to synth_ice40Clifford Wolf2015-05-262-2/+37
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* Improvements in BLIF front-endClifford Wolf2015-05-242-4/+51
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* improved ice40 SB_IO sim modelClifford Wolf2015-05-231-16/+9
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* Improved "flatten" handlings of inout portsClifford Wolf2015-05-231-2/+26
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* Added simple $dlatch support to opt_rmdffClifford Wolf2015-05-231-0/+35
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* Added ice40 SB_IO sim modelClifford Wolf2015-05-231-1/+46
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* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2015-05-221-19/+23
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| * Some fixes for $mem in verilog back-endClifford Wolf2015-05-201-19/+23
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* | preserve used $-wires with init attribute in opt_cleanClifford Wolf2015-05-221-1/+1
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* bugfix in blif front-endClifford Wolf2015-05-182-6/+6
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* added vloghtb test_febe.shClifford Wolf2015-05-172-0/+49
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* Improved .latch support in BLIF front-endClifford Wolf2015-05-171-3/+30
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* Added read_blif commandClifford Wolf2015-05-172-1/+33
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* Generalized blifparse APIClifford Wolf2015-05-173-21/+31
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* abc/blifparse files reorganizationClifford Wolf2015-05-177-8/+9
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* Verific build fixesClifford Wolf2015-05-175-7/+7
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* Added .barbuf support to abc BLIF parserClifford Wolf2015-05-131-0/+20
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* changed file() to open() in python scriptsClifford Wolf2015-05-114-11/+11
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* Merge pull request #63 from wluker/verilog-backend-memClifford Wolf2015-05-111-1/+2
|\ | | | | Fixed bug in $mem cell verilog code generation.
| * Fixed bug in $mem cell verilog code generation.luke whittlesey2015-05-111-11/+12
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* | Disabled broken $mem support in verilog backendClifford Wolf2015-05-101-11/+11
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* Merge pull request #62 from wluker/verilog-backend-memClifford Wolf2015-05-101-1/+164
|\ | | | | Added support for $mem cells in the verilog backend.
| * Made changes recommended by Clifford Wolf ...luke whittlesey2015-05-101-22/+11
| | | | | | | | | | | | Removed bit_check_equal(), used RTLIL::SigBit for individual bits, used dict<> instead of std::map, and used RTLIL::SigSpec instead of std::vector.
| * Verilog backend for $mem cells should now be able to handle differentluke whittlesey2015-05-081-50/+105
| | | | | | | | write-enable bits and RD_TRANSPARENT parameter settings.
| * Added support for $mem cells in the verilog backend.luke whittlesey2015-05-071-1/+120
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* Fixed memory_unpack for initialized memoriesClifford Wolf2015-04-291-0/+17
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* Preserve important attributes in splitnetsClifford Wolf2015-04-291-0/+13
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* Added $eq/$neq -> $logic_not/$reduce_bool optimizationClifford Wolf2015-04-294-1/+38
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* ice40_opt bugfixClifford Wolf2015-04-272-6/+4
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* iCE40: SB_CARRY const fold -> unmap SB_LUTClifford Wolf2015-04-271-3/+44
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* Added simplemap $lut supportClifford Wolf2015-04-273-8/+27
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* Added iCE40 const folding support for SB_CARRYClifford Wolf2015-04-273-2/+134
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* Initialization support for all iCE40 bram modesClifford Wolf2015-04-268-28/+65
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* initialized iCE40 brams (mode 0)Clifford Wolf2015-04-255-54/+261
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* improved iCE40 SB_RAM40_4K simulation modelClifford Wolf2015-04-251-59/+83
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* Updated ABC to hg rev 779de2de1481Clifford Wolf2015-04-251-1/+1
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