| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | | | | | * | | | | | | split latches into separate checks | Miodrag Milanovic | 2019-10-04 | 2 | -41/+24 | |
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| | | | | | * | | | | | | check muxes per type | Miodrag Milanovic | 2019-10-04 | 2 | -42/+37 | |
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| | | | | | * | | | | | | check ff's separately | Miodrag Milanovic | 2019-10-04 | 2 | -26/+14 | |
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| | | | | | * | | | | | | Cleanup top modules and not used defines | Miodrag Milanovic | 2019-10-04 | 5 | -44/+5 | |
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| | | | | | * | | | | | | remove alu test | Miodrag Milanovic | 2019-10-04 | 2 | -36/+0 | |
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| | | | | | * | | | | | | Merge branch 'SergeyDegtyar/anlogic' of ↵ | Miodrag Milanovic | 2019-10-04 | 23 | -0/+536 | |
| | | | | | |\ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://github.com/SergeyDegtyar/yosys into mmicko/anlogic | |||||
| | | | | | | * \ \ \ \ \ | Merge branch 'master' into SergeyDegtyar/anlogic | Sergey | 2019-10-01 | 126 | -1686/+30035 | |
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| | | | | | | * | | | | | | | run-test.sh Move $x at end of line. | Sergey | 2019-10-01 | 1 | -1/+1 | |
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| | | | | | | * | | | | | | | Add new tests for Anlogic architecture | SergeyDegtyar | 2019-09-23 | 23 | -0/+536 | |
| | | | | | |/ / / / / / / | | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Problems/questions: - memory.ys: ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database. Why EG_LOGIC_DRAM16X4, not AL_LOGIC_BRAM? - Internal cell type $_TBUF_ is present. | |||||
| | | | | | | | * | | | | | hierarchy - proc reorder | Miodrag Milanovic | 2019-10-18 | 6 | -13/+15 | |
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| | | | | | | | * | | | | | FF should be initialized to 0 | Miodrag Milanovic | 2019-10-04 | 1 | -1/+3 | |
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| | | | | | | | * | | | | | Split mux tests per type | Miodrag Milanovic | 2019-10-04 | 2 | -38/+36 | |
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| | | | | | | | * | | | | | Split latch check | Miodrag Milanovic | 2019-10-04 | 2 | -45/+24 | |
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| | | | | | | | * | | | | | Add missing latch mapping | Miodrag Milanovic | 2019-10-04 | 1 | -0/+12 | |
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| | | | | | | | * | | | | | split rest od ff's | Miodrag Milanovic | 2019-10-04 | 3 | -30/+17 | |
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| | | | | | | | * | | | | | Separate check for ff's types | Miodrag Milanovic | 2019-10-04 | 2 | -47/+48 | |
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| | | | | | | | * | | | | | Cleaned tests | Miodrag Milanovic | 2019-10-04 | 5 | -49/+4 | |
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| | | | | | | | * | | | | | Remove not needed tests | Miodrag Milanovic | 2019-10-04 | 6 | -75/+0 | |
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| | | | | | | | * | | | | | Merge branch 'SergeyDegtyar/efinix' of ↵ | Miodrag Milanovic | 2019-10-04 | 31 | -0/+710 | |
| | | | | | | |/| | | | | | | | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://github.com/SergeyDegtyar/yosys into mmicko/efinix | |||||
| | | | | | | | * | | | | | run-test.sh Move $x at end of line. | Sergey | 2019-10-01 | 1 | -1/+1 | |
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| | | | | | | | * | | | | | Merge branch 'master' into SergeyDegtyar/efinix | Sergey | 2019-10-01 | 126 | -1686/+30035 | |
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| | | | | | | | * | | | | | Add new tests for Efinix architecture. | SergeyDegtyar | 2019-09-23 | 31 | -0/+710 | |
| | | | | | |_|/ / / / / | | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Problems/questions: - fsm.ys. equiv_opt -assert failed because of unproven cells; - latches.ys,tribuf.ys - internal cells present; - memory.ys - sat called with -verify and proof did fail. | |||||
| * | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-10-08 | 14 | -138/+539 | |
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| | * | | | | | | | | | | Revert "Add test that is expecting to fail" | Eddie Hung | 2019-10-08 | 1 | -20/+0 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit c28d4b804720c2cf0086e921748219150e9631b5. | |||||
| | * | | | | | | | | | | Revert "Be mindful that sigmap(wire) could have dupes when checking \init" | Eddie Hung | 2019-10-08 | 1 | -4/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit f46ac1df9f8847dac9d9851f2f948d93a1064ff1. | |||||
| | * | | | | | | | | | | Merge pull request #1432 from YosysHQ/eddie/fix1427 | Eddie Hung | 2019-10-08 | 4 | -50/+145 | |
| | |\ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | Refactor peepopt_dffmux and be sensitive to \init when trimming | |||||
| | | * | | | | | | | | | | Use `sat -tempinduct` and comments for why equiv_opt not sufficient | Eddie Hung | 2019-10-03 | 1 | -1/+8 | |
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| | | * | | | | | | | | | | Fix broken CI, check reset even for constants, trim rstmux | Eddie Hung | 2019-10-02 | 2 | -25/+28 | |
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| | | * | | | | | | | | | | Fix test | Eddie Hung | 2019-10-02 | 1 | -2/+12 | |
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| | | * | | | | | | | | | | Merge branch 'eddie/fix_sat_init' into eddie/fix1427 | Eddie Hung | 2019-10-02 | 2 | -1/+24 | |
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| | | | * | | | | | | | | | | Be mindful that sigmap(wire) could have dupes when checking \init | Eddie Hung | 2019-10-02 | 1 | -1/+4 | |
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| | | | * | | | | | | | | | | Add test that is expecting to fail | Eddie Hung | 2019-10-02 | 1 | -0/+20 | |
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| | | * | | | | | | | | | | | Update test | Eddie Hung | 2019-10-02 | 1 | -13/+3 | |
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| | | * | | | | | | | | | | | Refactor peepopt_dffmux and be sensitive to \init when trimming | Eddie Hung | 2019-10-02 | 1 | -32/+63 | |
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| | | * | | | | | | | | | | | Add test | Eddie Hung | 2019-10-02 | 1 | -0/+31 | |
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| | * | | | | | | | | | | | | Merge pull request #1433 from YosysHQ/eddie/equiv_opt_async2sync | Eddie Hung | 2019-10-08 | 3 | -13/+19 | |
| | |\ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | async2sync to be called by equiv_opt only when -async2sync given | |||||
| | | * | | | | | | | | | | | | Add -async2sync to help text as per @daveshah1 | Eddie Hung | 2019-10-04 | 1 | -1/+4 | |
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| | | * | | | | | | | | | | | | Restore part of doc | Eddie Hung | 2019-10-03 | 1 | -1/+2 | |
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| | | * | | | | | | | | | | | | Disable equiv check for ice40 latches | Eddie Hung | 2019-10-03 | 1 | -6/+3 | |
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| | | * | | | | | | | | | | | | Add new -async2sync option | Eddie Hung | 2019-10-03 | 1 | -1/+11 | |
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| | | * | | | | | | | | | | | | Use equiv_opt -async2sync for xilinx | Eddie Hung | 2019-10-03 | 1 | -3/+1 | |
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| | | * | | | | | | | | | | | | Revert "equiv_opt to call async2sync when not -multiclock like SymbiYosys" | Eddie Hung | 2019-10-03 | 1 | -2/+0 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit a39505e329cc05dbd4ad624a1cf0f6caf664fd9a. | |||||
| | | * | | | | | | | | | | | | Revert "Update doc for equiv_opt" | Eddie Hung | 2019-10-03 | 1 | -3/+2 | |
| | | |/ / / / / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit a274b7cc86d4f64541d3d2903b4eeed4616ab1d8. | |||||
| | * | | | | | | | | | | | | Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9 | Eddie Hung | 2019-10-08 | 34 | -309/+316 | |
| | |\ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename abc_* names/attributes to more precisely be abc9_* | |||||
| | | * \ \ \ \ \ \ \ \ \ \ \ | Merge branch 'master' into eddie/abc_to_abc9 | Eddie Hung | 2019-10-04 | 8 | -185/+33 | |
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| | * | \ \ \ \ \ \ \ \ \ \ \ \ | Merge pull request #1438 from YosysHQ/eddie/xilinx_dsp_comments | Eddie Hung | 2019-10-08 | 5 | -72/+364 | |
| | |\ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add notes and comments for xilinx_dsp | |||||
| | | * | | | | | | | | | | | | | | Missed this | Eddie Hung | 2019-10-05 | 1 | -3/+4 | |
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| | | * | | | | | | | | | | | | | | Add comment on why we have to match for clock-enable/reset muxes | Eddie Hung | 2019-10-05 | 3 | -3/+11 | |
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| | | * | | | | | | | | | | | | | | Add note on pattern detector | Eddie Hung | 2019-10-05 | 1 | -3/+7 | |
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| | | * | | | | | | | | | | | | | | Add comment on why partial multipliers are 18x18 | Eddie Hung | 2019-10-04 | 1 | -4/+8 | |
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