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| | * greenpak4: removed unused MISO pin from GP_SPIAndrew Zonenberg2016-12-211-1/+0
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| | * greenpak4: Removed SPI_BUFFER parameterAndrew Zonenberg2016-12-201-1/+0
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| | * greenpak4: replaced MOSI/MISO with single one-way SDAT pinAndrew Zonenberg2016-12-201-2/+1
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| | * greenpak4: Changed port names on GP_SPI for clarityAndrew Zonenberg2016-12-201-4/+4
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| | * greenpak4: Initial implementation of GP_SPI cellAndrew Zonenberg2016-12-201-0/+27
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| | * Merge https://github.com/cliffordwolf/yosysAndrew Zonenberg2016-12-172-1/+61
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* | | Added "verilog_defines" commandClifford Wolf2016-12-151-0/+60
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* | | Bugfix in comment handlingClifford Wolf2016-12-131-1/+1
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| | * greenpak4: Updated GP_DCMP cell modelAndrew Zonenberg2016-12-171-2/+20
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| | * greenpak: Fixes to GP_DCMP* blocks. Added GP_CLKBUF.Andrew Zonenberg2016-12-161-5/+10
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| | * greenpak4: Initial version of GP_DCMP skeleton (not yet usable). Changed ↵Andrew Zonenberg2016-12-151-5/+24
| | | | | | | | | | | | interface to GP_DCMPMUX
| | * greenpak4: More fixups of GP_DCMPx cellsAndrew Zonenberg2016-12-151-9/+3
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| | * greenpak4: And another typo :(Andrew Zonenberg2016-12-151-1/+1
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| | * greenpak4: Fixed another typoAndrew Zonenberg2016-12-151-1/+1
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| | * greenpak4: Fixed typoAndrew Zonenberg2016-12-151-1/+1
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| | * greenpak4: Cleaned up trailing spaces in cells_simAndrew Zonenberg2016-12-141-60/+60
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| | * greenpak4: Added GP_DCMPREF / GP_DCMPMUXAndrew Zonenberg2016-12-141-0/+23
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| | * Merge https://github.com/cliffordwolf/yosysAndrew Zonenberg2016-12-127-0/+153
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* | | Added $anyconst support to AIGER back-endClifford Wolf2016-12-111-0/+7
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* | | Merge branch 'LSS-USP-unit-test-structure'Clifford Wolf2016-12-116-0/+146
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| * | Some minor CodingReadme changes in unit test sectionClifford Wolf2016-12-111-10/+4
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| * | Build hotfix in tests/unit/MakefileClifford Wolf2016-12-111-1/+1
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| * | Improved unit test structurerodrigosiqueira2016-12-103-16/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: rodrigosiqueira <rodrigosiqueiramelo@gmail.com> Signed-off-by: chaws <18oliveira.charles@gmail.com> * Merged run-all-unitest inside unit-test target * Fixed Makefile dependencies * Updated documentation about unit test
| * | Added explanation about configure and create testrodrigosiqueira2016-12-041-0/+75
| | | | | | | | | | | | Added explanation about configure unit test environment and how to add new unit tests
| * | Added required structure to implement unit testsrodrigosiqueira2016-12-045-0/+73
|/ / | | | | | | | | | | | | | | | | | | Added modifications inside the main Makefile to refers the unit test Makefile. Added separated Makefile only for compiling unit tests. Added simple example of unit test. Signed-off-by: Charles Oliveira <18oliveira.charles@gmail.com> Signed-off-by: Pablo Alejandro <pabloabur@usp.br> Signed-off-by: Rodrigo Siqueira <siqueira@ime.usp.br>
| * Added GP_PWRDET block, BANDWIDTH_KHZ parameter to GP_ABUFAndrew Zonenberg2016-12-111-1/+9
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| * greenpak4: Added support for inferred input/output inverters on latchesAndrew Zonenberg2016-12-101-4/+17
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| * greenpak4: Can now techmap inferred D latches (without set/reset or output ↵Andrew Zonenberg2016-12-103-0/+17
| | | | | | | | inverter)
| * greenpak4: Inverted D latch cells now have nQ instead of Q as output port ↵Andrew Zonenberg2016-12-101-15/+15
| | | | | | | | name for consistency
| * Added GP_DLATCH and GP_DLATCHIAndrew Zonenberg2016-12-051-0/+18
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| * Initial implementation of techlib support for GreenPAK latches. ↵Andrew Zonenberg2016-12-052-0/+120
| | | | | | | | Instantiation only, no behavioral inference yet.
| * Updated help text for synth_greenpak4Andrew Zonenberg2016-12-051-0/+2
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* Added $assert/$assume support to AIGER back-endClifford Wolf2016-12-033-13/+54
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* Improved yosys-smtbmc default -t/--assume-skipped for --cex and --aigClifford Wolf2016-12-031-2/+15
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* Updated ABV to hg rev 8b555d9e67cfClifford Wolf2016-12-011-1/+1
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* Added examples/aiger/Clifford Wolf2016-12-014-0/+53
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* Added "yosys-smtbmc --aig"Clifford Wolf2016-12-011-6/+127
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* Added support for partially initialized regs to smt2 back-endClifford Wolf2016-12-011-3/+15
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* Added "write_aiger -zinit -symbols -vmap"Clifford Wolf2016-12-011-30/+139
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* Added "write_aiger" commandClifford Wolf2016-11-302-0/+398
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* Added "design -reset-vlog"Clifford Wolf2016-11-301-7/+32
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* Improved equiv_purge log outputClifford Wolf2016-11-291-1/+1
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* Bugfix in smt2 back-end for pure checker modulesClifford Wolf2016-11-281-0/+4
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* Added support for macros as include file namesClifford Wolf2016-11-281-0/+2
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* Bugfix in "read_verilog -D NAME=VAL" handlingClifford Wolf2016-11-281-3/+3
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* Removed shebang line from smtio.py, fixes #279Clifford Wolf2016-11-271-1/+0
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* Added wire start_offset and upto handling BLIF back-endClifford Wolf2016-11-231-1/+1
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* Added wire start_offset and upto handling to splitnets cmdClifford Wolf2016-11-231-2/+8
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* Merge pull request #274 from oldtopman/lcursesClifford Wolf2016-11-221-0/+5
|\ | | | | Added optional flag for linking curses with readline.
| * Added optional flag for linking curses with readline.oldtopman2016-11-211-0/+5
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