| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Further improve cover() support | Clifford Wolf | 2017-02-04 | 3 | -8/+16 |
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| * | Add $cover cell type and SVA cover() support | Clifford Wolf | 2017-02-04 | 14 | -9/+38 |
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| * | Add assert/assume support to verific front-end | Clifford Wolf | 2017-02-04 | 2 | -625/+687 |
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| * | Update ABC to hg rev fe96921e5d50 | Clifford Wolf | 2017-02-01 | 1 | -1/+1 |
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| * | Update ABC scripts to use "&nf" instead of "map" | Clifford Wolf | 2017-02-01 | 1 | -3/+3 |
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| * | Merge branch 'C-Elegans-opt_compare_pr' | Clifford Wolf | 2017-01-31 | 1 | -0/+120 |
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| | * | Fix indenting and log messages in code merged from opt_compare_pr | Clifford Wolf | 2017-01-31 | 1 | -102/+120 |
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| | * | Merge branch 'opt_compare_pr' of https://github.com/C-Elegans/yosys into ↵ | Clifford Wolf | 2017-01-31 | 1 | -1/+103 |
| |/| | | | | | | | C-Elegans-opt_compare_pr | ||||
| | * | Refactor and generalize the comparision optimization | C-Elegans | 2017-01-30 | 1 | -22/+42 |
| | | | | | | | | | | | | | | | | | Generalizes the optimization to: a < C, a >= C, C > a, C <= a | ||||
| | * | Do not use b.as_int() in calculation of bit set | C-Elegans | 2017-01-21 | 1 | -8/+29 |
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| | * | Optimize compares to powers of 2 | C-Elegans | 2017-01-16 | 4 | -81/+61 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove opt_compare and put comparison pass in opt_expr assuming a [7:0] is unsigned a >= (1<<x) becomes |a[7:x] a < (1<<x) becomes !a[7:x] Additionally: a >= 0 becomes constant true, a < 0 becomes constant false delete opt_compare.cc revert opt.cc to commit b7cfb7dbd (remove opt_compare step) | ||||
| | * | Fix issue #269, optimize signed compare with 0 | C-Elegans | 2017-01-15 | 3 | -0/+81 |
| | | | | | | | | | | | | | | | | | add opt_compare pass and add it to opt for a < 0: if a is signed, replace with a[max_bit-1] for a >= 0: if a is signed, replace with ~a[max_bit-1] | ||||
| * | | Improve opt_rmdff support for $dlatch cells | Clifford Wolf | 2017-01-31 | 1 | -4/+22 |
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| * | | Add "yosys-smtbmc --aig <aim_filename>:<aiw_filename>" support | Clifford Wolf | 2017-01-30 | 1 | -5/+14 |
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| * | | Add $ff and $_FF_ support to equiv_simple | Clifford Wolf | 2017-01-30 | 1 | -2/+2 |
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| * | | Add "yosys-smtbmc --aig-noheader" and AIGER mem init support | Clifford Wolf | 2017-01-28 | 2 | -8/+55 |
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| * | | Be more conservative with merging large cells into FSMs | Clifford Wolf | 2017-01-26 | 1 | -3/+17 |
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| * | | Add warnings for quickly growing FSM table size in fsm_expand | Clifford Wolf | 2017-01-26 | 1 | -0/+10 |
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| * | | Merge branch 'master' of github.com:cliffordwolf/yosys | Clifford Wolf | 2017-01-26 | 2 | -4/+1 |
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| | * | | Fix RTLIL::Memory::start_offset initialization | Clifford Wolf | 2017-01-25 | 1 | -0/+1 |
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| | * | | Merge pull request #293 from thoughtpolice/minor-cleanup | Clifford Wolf | 2017-01-16 | 1 | -4/+0 |
| | |\ \ | | | | | | | | | Delete some dead code in the Hierarchy pass | ||||
| | | * | | passes/hierarchy: delete some dead code | Austin Seipp | 2017-01-15 | 1 | -4/+0 |
| | |/ / | | | | | | | | | | Signed-off-by: Austin Seipp <aseipp@pobox.com> | ||||
| * / / | Add "enum" and "typedef" lexer support | Clifford Wolf | 2017-01-17 | 2 | -1/+4 |
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| * / | Fix bug in AstNode::mem2reg_as_needed_pass2() | Clifford Wolf | 2017-01-15 | 1 | -0/+2 |
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| * | Fix $initstate handling bug in yosys-smtbmc | Clifford Wolf | 2017-01-11 | 1 | -0/+2 |
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| * | Update ABC to hg id f8cadfe3861f | Clifford Wolf | 2017-01-11 | 1 | -3/+3 |
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| * | Updated ABC to hg id 38b26a543f1d | Clifford Wolf | 2017-01-08 | 1 | -1/+1 |
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| * | Fixed handling of local memories in functions | Clifford Wolf | 2017-01-05 | 1 | -2/+2 |
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| * | Added "check -initdrv" | Clifford Wolf | 2017-01-04 | 1 | -3/+82 |
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| * | Added handling of local memories and error for local decls in unnamed blocks | Clifford Wolf | 2017-01-04 | 1 | -1/+10 |
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| * | Implicitly set "yosys-smtbmc --noprogress" on windows | Clifford Wolf | 2017-01-04 | 1 | -3/+4 |
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| * | Fixed typo in tests/simple/arraycells.v | Clifford Wolf | 2017-01-04 | 1 | -1/+1 |
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| * | Fixed "yosys-smtbmc --noprogress" | Clifford Wolf | 2017-01-04 | 1 | -1/+1 |
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| * | Added Verilog $rtoi and $itor support | Clifford Wolf | 2017-01-03 | 1 | -24/+30 |
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| * | Handle "always 1" like "always -1" in .smtc files | Clifford Wolf | 2017-01-02 | 1 | -7/+5 |
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| * | Added cell port resizing to hierarchy pass | Clifford Wolf | 2017-01-01 | 1 | -0/+56 |
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| * | Updated ABC to hg id 55cd83f432c0 | Clifford Wolf | 2016-12-31 | 1 | -1/+1 |
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| * | Bugfix in RTLIL::SigSpec::remove2() | Clifford Wolf | 2016-12-31 | 1 | -3/+4 |
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| * | Updated ABC to hg id 8c6a635f7a20 | Clifford Wolf | 2016-12-29 | 1 | -1/+1 |
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| * | Improved write_json help message | Clifford Wolf | 2016-12-29 | 1 | -0/+4 |
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| * | Updated ABC to hg id f591c081d5e7 | Clifford Wolf | 2016-12-26 | 1 | -1/+1 |
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| * | Merge pull request #284 from azonenberg/master | Clifford Wolf | 2016-12-24 | 6 | -65/+328 |
| |\ | | | | | greenpak4: Support for many new cell types | ||||
| | * | Merge pull request #1 from azonenberg-hk/master | Andrew Zonenberg | 2016-12-23 | 19 | -70/+586 |
| | |\ | | | | | | | Pull changes from HK trip | ||||
| | | * | Merge https://github.com/cliffordwolf/yosys | Andrew Zonenberg | 2016-12-23 | 5 | -4/+44 |
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| * | | | Simplified log_spacer() code | Clifford Wolf | 2016-12-23 | 1 | -6/+2 |
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| * | | | Added "yosys -W regex" | Clifford Wolf | 2016-12-22 | 3 | -2/+44 |
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| * | | | Added AIGER back-end to automatic back-end detection | Clifford Wolf | 2016-12-21 | 1 | -0/+2 |
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| * | | | Updated ABC to hg rev a4872e22c646 | Clifford Wolf | 2016-12-21 | 1 | -1/+1 |
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| * | | | Updated ABC to hg rev 8bab2eedbba4 | Clifford Wolf | 2016-12-21 | 1 | -1/+1 |
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| | | * | greenpak4: Added INT pin to GP_SPI | Andrew Zonenberg | 2016-12-21 | 1 | -1/+3 |
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index : iCE40/yosys | |
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