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| * | | | | | | | | | | | | | | | | | | ConsistencyEddie Hung2019-12-271-1/+1
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| * | | | | | | | | | | | | | | | | | | Cope with abc9_arrival as stringEddie Hung2019-12-271-6/+15
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| * | | | | | | | | | | | | | | | | | | Update some abc9_arrival times, add abc9_required timesEddie Hung2019-12-273-24/+220
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* | | | | | | | | | | | | | | | | | | | Add opt_lut_ins pass. (#1673)Marcelina Kościelnicka2020-02-0310-4/+367
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* | | | | | | | | | | | | | | | | | | Merge pull request #1516 from YosysHQ/dave/dotstarDavid Shah2020-02-026-6/+208
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sv: Add support for wildcard port connections (.*)
| * | | | | | | | | | | | | | | | | | | Update CHANGELOG and READMEDavid Shah2020-02-022-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | | | | | | | | | | | | | | | | sv: Improve handling of wildcard port connectionsDavid Shah2020-02-023-7/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | | | | | | | | | | | | | | | | sv: More tests for wildcard port connectionsDavid Shah2020-02-021-0/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | | | | | | | | | | | | | | | | hierarchy: Correct handling of wildcard port connections with default valuesDavid Shah2020-02-022-7/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | | | | | | | | | | | | | | | | sv: Add tests for wildcard port connectionsDavid Shah2020-02-021-0/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | | | | | | | | | | | | | | | | hierarchy: Resolve SV wildcard port connectionsDavid Shah2020-02-022-4/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | | | | | | | | | | | | | | | | sv: Add lexing and parsing of .* (wildcard port conns)David Shah2020-02-022-1/+6
|/ / / / / / / / / / / / / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | | | | | | | | | | | | | | Merge pull request #1647 from YosysHQ/dave/sprintfDavid Shah2020-02-023-93/+122
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ast: Add support for $sformatf system function
| * | | | | | | | | | | | | | | | | | | ast: Add support for $sformatf system functionDavid Shah2020-01-193-93/+122
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | | | | | | | | | | | | | | | Merge pull request #1657 from YosysHQ/dave/xilinx-dsp-multonlyDavid Shah2020-02-021-0/+7
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | synth_xilinx: add -dsp-multonly
| * | | | | | | | | | | | | | | | | | | | xilinx_dsp: Add multonly scratchpad var to bypassDavid Shah2020-02-011-0/+7
| |/ / / / / / / / / / / / / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | | | | | | | | | | | | | | | xilinx: use RAM32M/RAM64M for memories with two read portsMarcin Kościelnicki2020-02-021-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes inefficient LUT RAM usage for memories with one write and two read ports (commonly used as register files).
* | | | | | | | | | | | | | | | | | | | json: remove the 32-bit parameter special caseMarcin Kościelnicki2020-02-011-10/+28
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* | | | | | | | | | | | | | | | | | | Merge pull request #1668 from gsomlo/gls-abc9-externalEddie Hung2020-01-311-0/+1
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | abc9: Fix regression breaking support for use of ABCEXTERNAL
| * | | | | | | | | | | | | | | | | | | abc9: restore ability to use ABCEXTERNALGabriel Somlo2020-01-301-0/+1
|/ / / / / / / / / / / / / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
* | | | | | | | | | | | | | | | | | | Merge pull request #1667 from YosysHQ/clifford/verificnandClaire Wolf2020-01-301-0/+8
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|/ |/| | | | | | | | | | | | | | | | | | Add Verific support for OPER_REDUCE_NAND
| * | | | | | | | | | | | | | | | | | Add Verific support for OPER_REDUCE_NANDClaire Wolf2020-01-301-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <clifford@clifford.at>
* | | | | | | | | | | | | | | | | | | Merge pull request #1503 from YosysHQ/eddie/verific_helpClaire Wolf2020-01-301-8/+8
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | `verific` pass to print help message when command syntax error
| * \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ Merge remote-tracking branch 'origin/master' into eddie/verific_helpEddie Hung2020-01-27208-4938/+10113
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| * | | | | | | | | | | | | | | | | | | | verific: no help() when no YOSYS_ENABLE_VERIFICEddie Hung2020-01-271-4/+1
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| * | | | | | | | | | | | | | | | | | | | OopsEddie Hung2019-11-191-1/+1
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| * | | | | | | | | | | | | | | | | | | | Print help message for verific passEddie Hung2019-11-191-9/+12
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* | | | | | | | | | | | | | | | | | | | | Merge pull request #1654 from YosysHQ/eddie/sby_fix69Claire Wolf2020-01-301-0/+6
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | |_|_|/ / / / / / / / / / / / / / / / / / |/| | | | | | | | | | | | | | | | | | | | verific: unflatten struct ports
| * | | | | | | | | | | | | | | | | | | | verific: also unflatten for 'hierarchy' flow as per @cliffordwolfEddie Hung2020-01-271-0/+3
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| * | | | | | | | | | | | | | | | | | | | verific: unflatten struct portsEddie Hung2020-01-241-0/+3
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* | | | | | | | | | | | | | | | | | | | Merge branch 'vector_fix' of https://github.com/Kmanfi/yosysClaire Wolf2020-01-291-1/+3
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Also some minor fixes to the original PR.
| * | | | | | | | | | | | | | | | | | | | Fix input vector for reduce cells. Infinite loop fixed.Kaj Tuomi2017-10-171-0/+2
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| * | | | | | | | | | | | | | | | | | | | Merge branch 'master' of https://github.com/cliffordwolf/yosys into vector_fixKaj Tuomi2017-10-173-1/+54
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| * | | | | | | | | | | | | | | | | | | | | Add Verific fairness/liveness supportClifford Wolf2017-10-121-11/+32
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* | | | | | | | | | | | | | | | | | | | | | Merge pull request #1662 from YosysHQ/dave/opt-reduce-move-checkClaire Wolf2020-01-291-1/+2
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | opt_reduce: Call check() per run rather than per optimised cell
| * | | | | | | | | | | | | | | | | | | | | | opt_reduce: Call check() per run rather than per optimised cellDavid Shah2020-01-281-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1665 from YosysHQ/clifford/edifkeepClaire Wolf2020-01-291-9/+34
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Preserve wires with keep attribute in EDIF back-end
| * | | | | | | | | | | | | | | | | | | | | | | Preserve wires with keep attribute in EDIF back-endClaire Wolf2020-01-291-9/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <clifford@clifford.at>
* | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1659 from YosysHQ/clifford/experimentalClaire Wolf2020-01-296-4/+56
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add log_experimental() and experimental() API and "yosys -x"
| * | | | | | | | | | | | | | | | | | | | | | | | Improve logging use of experimental featuresClaire Wolf2020-01-283-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <clifford@clifford.at>
| * | | | | | | | | | | | | | | | | | | | | | | | Add log_experimental() and experimental() API and "yosys -x"Claire Wolf2020-01-276-4/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <clifford@clifford.at>
* | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1510 from pumbor/masterN. Engelhardt2020-01-291-0/+13
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | handle anonymous unions to fix #1080
| * | | | | | | | | | | | | | | | | | | | | | | | | handle anonymous unions to fix #1080Patrick Eibl2019-11-211-0/+13
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* | | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1559 from YosysHQ/efinix_test_fixMiodrag Milanović2020-01-291-1/+1
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix for non-deterministic test
| * | | | | | | | | | | | | | | | | | | | | | | | | | Updated test to use assert-maxMiodrag Milanovic2020-01-281-1/+1
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| * | | | | | | | | | | | | | | | | | | | | | | | | | Fix for non-deterministic testMiodrag Milanovic2019-12-071-1/+1
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* | | | | | | | | | | | | | | | | | | | | | | | | | | Add "help -all" and "help -celltypes" sanity testEddie Hung2020-01-281-0/+2
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* | | | | | | | | | | | | | | | | | | | | | | | | | | synth_xilinx: cleanup helpEddie Hung2020-01-281-6/+4
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* | | | | | | | | | | | | | | | | | | | | | | | | | | synth_xilinx: fix help when no active_design; fixes #1664Eddie Hung2020-01-281-2/+3
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* | | | | | | | | | | | | | | | | | | | | | | | | | | xilinx: Add simulation model for DSP48 (Virtex 4).Marcin Kościelnicki2020-01-296-45/+534
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