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* | Fixed simlib.v model for $memClifford Wolf2014-07-171-15/+15
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* | Added support for bit/part select to mem2reg rewriterClifford Wolf2014-07-172-0/+30
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* | Added support for constant bit- or part-select for memory writesClifford Wolf2014-07-172-9/+56
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* | Improved opt_reduce handling of mem wr_en mux bitsClifford Wolf2014-07-171-5/+18
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* | Fixed RTLIL::SigSpec::append_bit() for appending constantsClifford Wolf2014-07-171-2/+3
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* | Added support for "blackbox" attribute to iopadmapClifford Wolf2014-07-171-1/+1
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* | Added support for "blackbox" attribute to flatten/techmapClifford Wolf2014-07-171-1/+4
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* | Added "inout" ports support to read_libertyClifford Wolf2014-07-161-1/+6
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* | Set blackbox attribute in "read_liberty -lib"Clifford Wolf2014-07-161-0/+3
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* | Fixed spelling of "direction" in read_liberty messagesClifford Wolf2014-07-161-2/+2
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* | Merged new $mem/$memwr WR_EN interfaceClifford Wolf2014-07-1610-82/+216
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| * | Changed tests/techmap/mem_simple_4x1_map for new $mem/$memwr WR_EN interfaceClifford Wolf2014-07-161-2/+13
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| * | improved opt_reduce for $mem/$memwr WR_EN multiplexersClifford Wolf2014-07-161-0/+80
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| * | changes in verilog frontend for new $mem/$memwr WR_EN interfaceClifford Wolf2014-07-162-7/+6
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| * | Changes to "memory" pass for new $memwr/$mem WR_EN interfaceClifford Wolf2014-07-163-38/+56
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| * | Updated simlib to new $mem/$memwr interfaceClifford Wolf2014-07-161-30/+55
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| * | Changed the $mem/$memwr WR_EN input to a per-data-bit enable signalClifford Wolf2014-07-162-5/+6
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* | Added note to "make test": use git checkout of iverilogClifford Wolf2014-07-165-5/+15
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* | Added passing of various options to vhdl2verilogClifford Wolf2014-07-121-5/+36
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* | Use "verilog -sv" to parse .sv filesClifford Wolf2014-07-111-0/+2
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* | Fixed processing of initial values for block-local variablesClifford Wolf2014-07-111-0/+5
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* | now ignore init attributes on non-register wires in sat commandClifford Wolf2014-07-053-4/+43
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* | fixed parsing of constant with comment between size and valueClifford Wolf2014-07-022-0/+14
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* | small changes in presentationClifford Wolf2014-07-021-5/+2
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* | Tiny fix in presentationClifford Wolf2014-06-291-1/+1
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* | Progress in presentationClifford Wolf2014-06-292-0/+97
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* | Added links to some liberty files to READMEClifford Wolf2014-06-281-0/+8
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* | Progress in presentationClifford Wolf2014-06-267-79/+105
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* | Fixed handling of mixed real/int ternary expressionsClifford Wolf2014-06-252-3/+22
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* | More found_real-related fixes to AstNode::detectSignWidthWorkerClifford Wolf2014-06-241-6/+6
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* | Progress in presentationClifford Wolf2014-06-227-42/+503
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* | Little steps in realmath test benchClifford Wolf2014-06-212-2/+8
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* | fixed signdness detection for expressions with realsClifford Wolf2014-06-211-2/+8
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* | fixed typoClifford Wolf2014-06-211-1/+1
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* | Progress in presentationClifford Wolf2014-06-219-23/+188
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* | Do not create $dffsr cells with no-op resets in proc_dffClifford Wolf2014-06-191-0/+5
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* | Added test case for AstNode::MEM2REG_FL_CMPLX_LHSClifford Wolf2014-06-171-0/+12
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* | Added AstNode::MEM2REG_FL_CMPLX_LHSClifford Wolf2014-06-172-0/+23
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* | Improved handling of relational op of real valuesClifford Wolf2014-06-172-12/+17
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* | Little steps in realmath test benchClifford Wolf2014-06-162-0/+3
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* | Improved ternary support for real valuesClifford Wolf2014-06-161-13/+24
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* | Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012Clifford Wolf2014-06-162-0/+11
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* | Fixed parsing of TOK_INTEGER (implies TOK_SIGNED)Clifford Wolf2014-06-161-5/+11
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* | Added found_real feature to AstNode::detectSignWidthClifford Wolf2014-06-162-6/+11
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* | Added more calls to "hierarchy" to README fileClifford Wolf2014-06-151-3/+8
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* | Removed long running tests from tests/simple/realexpr.v (replaced by ↵Clifford Wolf2014-06-151-55/+0
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* | Added tests/realmath to "make test"Clifford Wolf2014-06-155-4/+6
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* | Improved AstNode::realAsConst for large numbersClifford Wolf2014-06-151-1/+1
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* | Improved realmath test benchClifford Wolf2014-06-152-5/+13
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* | Improved parsing of large integer constantsClifford Wolf2014-06-151-11/+28
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