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Added "extract -map %<design_name>"
Clifford Wolf
2014-02-20
1
-10
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+30
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Added "design -push" and "design -pop"
Clifford Wolf
2014-02-20
2
-8
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+49
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Progress in presentation
Clifford Wolf
2014-02-20
5
-0
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+207
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*
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Added connwrappers command
Clifford Wolf
2014-02-20
2
-0
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+206
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*
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Cleanups in handling of read_verilog -defer and -icells
Clifford Wolf
2014-02-20
1
-6
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+7
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Progress in presentation
Clifford Wolf
2014-02-20
10
-10
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+152
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Added vcd2txt.pl and txt2tikztiming.py (tests/tools/...)
Clifford Wolf
2014-02-19
2
-0
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+170
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Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf
2014-02-18
2
-50
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+99
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*
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Added "sat -dump_cnf"
Clifford Wolf
2014-02-18
1
-5
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+34
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Coding style corrections in SatHelper::dump_model_to_vcd()
Clifford Wolf
2014-02-18
1
-31
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+31
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*
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Improved non-verbose ezSAT::printDIMACS() format
Clifford Wolf
2014-02-18
1
-1
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+6
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*
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Added "sat -initsteps"
Clifford Wolf
2014-02-18
1
-14
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+29
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*
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Progress in presentation
Clifford Wolf
2014-02-18
6
-3
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+72
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*
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Added techmap support for _TECHMAP_CONNMAP_*_
Clifford Wolf
2014-02-18
1
-0
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+39
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*
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Added Verilog support for "`default_nettype none"
Clifford Wolf
2014-02-17
8
-8
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+31
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*
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Renamed "sat -dump_fail_to_vcd" to "sat -dump_vcd" and some minor cleanups
Clifford Wolf
2014-02-17
1
-5
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+9
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*
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Added "-dump_fail_to_vcd" argument to SAT solver
Andrew Zonenberg
2014-02-17
1
-0
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+114
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*
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Progress in presentation
Clifford Wolf
2014-02-17
3
-9
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+37
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*
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Better preserve wires when flattening (in comparison to techmap)
Clifford Wolf
2014-02-17
1
-12
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+12
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*
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Progress in presentation
Clifford Wolf
2014-02-16
5
-1
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+80
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*
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Added some additional checks to techmap
Clifford Wolf
2014-02-16
1
-0
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+14
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*
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Added CONSTMSK and CONSTVAL feature to techmap
Clifford Wolf
2014-02-16
1
-0
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+23
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*
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Fixed handling of "keep" attribute on wires in opt_clean
Clifford Wolf
2014-02-16
1
-2
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+2
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*
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Added a warning note about error reporting to read_verilog help message
Clifford Wolf
2014-02-16
1
-0
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+5
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*
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Progress in presentation
Clifford Wolf
2014-02-16
5
-1
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+79
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*
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Fixed use of selection in splitnets command
Clifford Wolf
2014-02-16
1
-1
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+1
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*
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Added recursion support to techmap
Clifford Wolf
2014-02-16
1
-260
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+262
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*
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Progress in presentation
Clifford Wolf
2014-02-16
6
-3
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+74
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*
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Progress in presentation
Clifford Wolf
2014-02-16
6
-1
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+114
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*
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Improved support for constant functions
Clifford Wolf
2014-02-16
1
-1
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+50
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*
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Now we are in Yoys 0.2.0+ development
Clifford Wolf
2014-02-16
2
-3
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+9
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*
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Tagging Yoys 0.2.0
Clifford Wolf
2014-02-16
2
-5
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+88
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Added != support for relational select pattern
Clifford Wolf
2014-02-16
1
-1
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+7
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*
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Added iopadmap -bits
Clifford Wolf
2014-02-15
1
-14
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+48
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*
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Added ff and latch support to read_liberty
Clifford Wolf
2014-02-15
1
-40
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+254
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*
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Bugfix in expression parser of read_liberty
Clifford Wolf
2014-02-15
1
-2
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+1
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*
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Fixed dfflibmap for cell libraries with no set-reset-ff
Clifford Wolf
2014-02-15
1
-1
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+1
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*
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Correctly convert constants to RTLIL (fixed undef handling)
Clifford Wolf
2014-02-15
1
-11
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+1
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*
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Added frontend (-f) option to autotest.sh
Clifford Wolf
2014-02-15
1
-5
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+8
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*
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Fixed opt_const handling of double invert with non-1 output width
Clifford Wolf
2014-02-15
1
-1
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+1
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*
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Added liberty frontend
Clifford Wolf
2014-02-15
2
-0
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+362
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*
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Be more conservative with new const-function code
Clifford Wolf
2014-02-14
1
-1
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+5
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*
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Added support for FOR loops in function calls in parameters
Clifford Wolf
2014-02-14
3
-0
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+43
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*
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Created basic support for function calls in parameter values
Clifford Wolf
2014-02-14
4
-49
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+184
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*
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Added abc -keepff option
Clifford Wolf
2014-02-14
1
-5
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+18
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*
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updated default ABC command strings
Clifford Wolf
2014-02-13
1
-4
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+4
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Updated ABC
Clifford Wolf
2014-02-13
2
-1
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+24
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Implemented read_verilog -defer
Clifford Wolf
2014-02-13
4
-66
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+109
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Removed double blanks in ABC default command sequences
Clifford Wolf
2014-02-13
1
-4
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+4
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*
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Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf
2014-02-13
3
-33
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+60
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