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* | | Fixed iCE40 SB_IO OUTPUT_ENABLE vs. outena_q handlingClifford Wolf2015-11-061-2/+2
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* | | Bugfix in mapping $tribuf to $_TBUF_Clifford Wolf2015-11-051-1/+1
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* | | Bugfix in memory_dffClifford Wolf2015-10-312-1/+27
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* | | Improvements in wreduceClifford Wolf2015-10-312-0/+34
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* | | Bugfix in Xilinx LUT mappingClifford Wolf2015-10-301-1/+1
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* | | Improved SigMap performanceClifford Wolf2015-10-283-5/+16
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* | | Improvements in new SigMapClifford Wolf2015-10-281-5/+16
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* | | Use mfp<> in equiv_markClifford Wolf2015-10-271-28/+4
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* | | Removed old SigMap implementationClifford Wolf2015-10-271-224/+0
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* | | Added hashlib::mfp and new SigMapClifford Wolf2015-10-273-0/+185
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* | | Improvements in equiv_structClifford Wolf2015-10-251-17/+62
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* | | Major refactoring of equiv_structClifford Wolf2015-10-252-93/+170
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* | | Import more std:: stuff into Yosys namespaceClifford Wolf2015-10-2539-161/+168
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* | | Added "equiv_add -cell"Clifford Wolf2015-10-252-34/+95
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* | | equiv_struct now creates equiv_merged attributesClifford Wolf2015-10-251-0/+3
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* | | Improvements in equiv_structClifford Wolf2015-10-241-1/+22
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* | | renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit()Clifford Wolf2015-10-248-34/+34
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* | | improvement in "stat"Clifford Wolf2015-10-241-1/+1
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* | | Fixed driver conflict handling (various cmds)Clifford Wolf2015-10-241-3/+12
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* | | equiv_purge bugfix, using SigChunk in Yosys namespaceClifford Wolf2015-10-245-5/+8
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* | | Fixed handling of driver-driver conflicts in wreduceClifford Wolf2015-10-243-9/+42
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* | | Added equiv_mark commandClifford Wolf2015-10-233-1/+265
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* | | Disabled "Skipping blackbox module" msg in show commandClifford Wolf2015-10-231-1/+1
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* | | Added support for ":" as comment symbol after ;-parsingClifford Wolf2015-10-231-1/+1
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* | | Also merge $equiv cells in equiv_structClifford Wolf2015-10-231-0/+1
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* | | Improvements in equiv_structClifford Wolf2015-10-231-11/+18
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* | | Added equiv_purgeClifford Wolf2015-10-222-0/+210
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* | | Added equiv_struct commandClifford Wolf2015-10-212-0/+188
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* | | Improved inout handling in equiv_makeClifford Wolf2015-10-211-1/+1
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* | | Progress on cell help messagesClifford Wolf2015-10-201-18/+114
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* | | Progress on cell help messagesClifford Wolf2015-10-173-54/+107
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* | | Progress in yosys-smtbmcClifford Wolf2015-10-151-4/+10
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* | | Fixed bug in verilog parserClifford Wolf2015-10-151-1/+1
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* | | Improvements in yosys-smtbmcClifford Wolf2015-10-153-2/+9
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* | | Bugfixes in handling of "keep" attribute on wiresClifford Wolf2015-10-152-2/+8
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* | | More "yosys-smtbmc -c" fixesClifford Wolf2015-10-142-9/+30
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* | | Fixed yosys-smtbmc -cClifford Wolf2015-10-141-2/+2
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* | | Added "prep" commandClifford Wolf2015-10-142-0/+157
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* | | Added more cell descriptionsClifford Wolf2015-10-141-0/+85
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* | | Added first help messages for cell typesClifford Wolf2015-10-146-6/+336
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* | | Added yosys-smtbmc copyrightClifford Wolf2015-10-143-1/+36
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* | | Improvements in yosys-smtbmcClifford Wolf2015-10-143-21/+38
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* | | Added yosys-smtbmcClifford Wolf2015-10-142-1/+20
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* | | Implemented smtbmc.py -iClifford Wolf2015-10-141-25/+60
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* | | Added smtbmc.pyClifford Wolf2015-10-134-0/+409
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* | | Added write_smt2 -wiresClifford Wolf2015-10-131-7/+15
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* | | Added examples/ top-level directoryClifford Wolf2015-10-1317-4/+7
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* | | SystemVerilog also has assume(), added implicit -D FORMALClifford Wolf2015-10-133-4/+5
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* | | Merge branch 'master' of https://github.com/rubund/yosysClifford Wolf2015-10-131-18/+18
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| * | | Use DESTDIR as defined in ↵Ruben Undheim2015-10-111-13/+13
| | | | | | | | | | | | | | | | | | | | | | | | https://www.gnu.org/prep/standards/html_node/DESTDIR.html This is needed for painless packaging of yosys