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* abc9 to replace $_NOT_ with $lutEddie Hung2019-02-191-4/+39
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* read_aiger to create sane $lut names, and rename when renaming driving wireEddie Hung2019-02-191-2/+11
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* Add commentEddie Hung2019-02-191-1/+2
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* Get rid of boost dep, fix the FIXMEs for Win32?Eddie Hung2019-02-191-14/+14
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* Get rid of debugging stuff in abc9Eddie Hung2019-02-161-6/+1
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* In read_xaiger, do not construct ConstEval for every LUTEddie Hung2019-02-161-1/+1
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* CleanupEddie Hung2019-02-161-4/+5
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* read_aiger to ignore output = input of same wire; also create new output for ↵Eddie Hung2019-02-161-2/+16
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* CleanupEddie Hung2019-02-161-2/+1
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* write_xaiger to support non-bit cell connections, and cope with COs for -OEddie Hung2019-02-161-13/+15
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* abc9 to write_aiger with -O option, and ignore dummy outputsEddie Hung2019-02-161-2/+8
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* write_aiger -O to write dummy output as __dummy_o__Eddie Hung2019-02-161-2/+5
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* abc9 to handle comb loops, cope with constant outputs, disconnect using new wireEddie Hung2019-02-161-4/+67
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* read_aiger to disable log_debugEddie Hung2019-02-161-1/+2
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* expose command to not skip 'internal' wires beginning with '$'Eddie Hung2019-02-161-1/+1
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* read_xaiger() to use f.read() not readsome()Eddie Hung2019-02-161-1/+2
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* abc9 to cope with non-wideports, count cells properlyEddie Hung2019-02-161-11/+54
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* Tidy up write_xaigerEddie Hung2019-02-161-8/+6
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* write_aiger() to perform CI/CO post-processing and fix symbolsEddie Hung2019-02-161-7/+17
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* read_aiger() to cope with constant outputs, mixed wideports, do cleaningEddie Hung2019-02-161-8/+130
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* Move lookup inside ifEddie Hung2019-02-151-2/+2
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* Fixes needed for DFF circuitsEddie Hung2019-02-151-4/+3
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* RefactorEddie Hung2019-02-151-29/+32
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* Cope with width != 1 when re-mapping cellsEddie Hung2019-02-151-11/+25
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* abc9 to stitch results with CI/CO properlyEddie Hung2019-02-151-16/+32
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* read_aiger with more asserts, and call cleanEddie Hung2019-02-151-4/+11
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* write_xaiger to cope with unknown cells by transforming them to CI/COEddie Hung2019-02-151-6/+44
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* More cleanupEddie Hung2019-02-141-15/+6
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* More cleanup of write_xaigerEddie Hung2019-02-141-73/+1
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* Get rid of formal stuff from xaiger backendEddie Hung2019-02-141-58/+0
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* synth_ice40 to have new -abc9 argEddie Hung2019-02-141-4/+12
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* Leave FIXME for cleanEddie Hung2019-02-131-3/+3
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* Use module->addLut()Eddie Hung2019-02-131-5/+1
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* Fix stitchingEddie Hung2019-02-131-4/+4
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* Use ConstEval to compute LUT masksEddie Hung2019-02-132-63/+69
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* Merge remote-tracking branch 'origin/read_aiger' into xaigEddie Hung2019-02-134-17/+12
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| * Missing headers for Xcode?Eddie Hung2019-02-121-0/+2
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| * Merge branch 'read_aiger' of github.com:eddiehung/yosys into read_aigerEddie Hung2019-02-121-3/+1
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| | * Do not break for constraintsEddie Hung2019-02-111-1/+0
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| | * No increment line_count for binary ANDsEddie Hung2019-02-111-1/+1
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| | * Do not ignore newline after AND in binary AIGEddie Hung2019-02-111-1/+0
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| * | Use module->add{Not,And}Gate() functionsEddie Hung2019-02-121-8/+2
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| * Merge remote-tracking branch 'origin/dff_init' into read_aigerEddie Hung2019-02-082-7/+7
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| | * Cope WIDTH of ff/latch cells is default of zeroEddie Hung2019-02-061-6/+6
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| | * Remove check for cell->name[0] == '$'Eddie Hung2019-02-061-1/+1
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* | | Merge https://github.com/YosysHQ/yosys into xaigEddie Hung2019-02-133-44/+47
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| * | | Fix sign handling of real constantsClifford Wolf2019-02-131-5/+4
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Merge pull request #802 from whitequark/write_verilog_async_mem_portsClifford Wolf2019-02-121-38/+41
| |\ \ \ | | | | | | | | | | write_verilog: correctly emit asynchronous transparent ports
| | * | | write_verilog: correctly emit asynchronous transparent ports.whitequark2019-01-291-38/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit fixes two related issues: * For asynchronous ports, clock is no longer added to domain list. (This would lead to absurd constructs like `always @(posedge 0)`. * The logic to distinguish synchronous and asynchronous ports is changed to correctly use or avoid clock in all cases. Before this commit, the following RTLIL snippet (after memory_collect) cell $memrd $2 parameter \MEMID "\\mem" parameter \ABITS 2 parameter \WIDTH 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 1 parameter \TRANSPARENT 1 connect \CLK 1'0 connect \EN 1'1 connect \ADDR \mem_r_addr connect \DATA \mem_r_data end would lead to invalid Verilog: reg [1:0] _0_; always @(posedge 1'h0) begin _0_ <= mem_r_addr; end assign mem_r_data = mem[_0_]; Note that there are two potential pitfalls remaining after this change: * For asynchronous ports, the \EN input and \TRANSPARENT parameter are silently ignored. (Per discussion in #760 this is the correct behavior.) * For synchronous transparent ports, the \EN input is ignored. This matches the behavior of the $mem simulation cell. Again, see #760.
| * | | | Merge pull request #806 from daveshah1/fsm_opt_no_resetClifford Wolf2019-02-121-1/+2
| |\ \ \ \ | | | | | | | | | | | | fsm_opt: Fix runtime error for FSMs without a reset state
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