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* Stray newlineEddie Hung2019-12-061-1/+0
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* write_xaiger to inst each cell type once, do not call techmap/aigmapEddie Hung2019-12-061-21/+25
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* techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaigerEddie Hung2019-12-063-0/+15
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* Merge pull request #1551 from whitequark/manual-cell-operandsClifford Wolf2019-12-053-43/+82
|\ | | | | Clarify semantics of comb cells, in particular shifts
| * kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr.whitequark2019-12-042-8/+26
| | | | | | | | | | | | | | Before this commit, these cells would accept any \B_SIGNED and in case of \B_SIGNED=1, would still treat the \B input as unsigned. Also fix the Verilog frontend to never emit such constructs.
| * manual: document behavior of many comb cells more precisely.whitequark2019-12-041-35/+56
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* | xilinx: Add tristate buffer mapping. (#1528)Marcin Kościelnicki2019-12-042-9/+16
| | | | | | Fixes #1225.
* | iopadmap: Refactor and fix tristate buffer mapping. (#1527)Marcin Kościelnicki2019-12-042-146/+196
| | | | | | | | | | | | | | The previous code for rerouting wires when inserting tristate buffers was overcomplicated and didn't handle all cases correctly (in particular, only cell connections were rewired — internal connections were not).
* | xilinx: Add models for LUTRAM cells. (#1537)Marcin Kościelnicki2019-12-043-624/+831
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* | Merge pull request #1524 from pepijndevos/gowindffinitClifford Wolf2019-12-035-114/+571
|\ \ | | | | | | Gowin: add and test DFF init values
| * | update testPepijn de Vos2019-12-031-2/+3
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| * | Use -match-init to not synth contradicting init valuesPepijn de Vos2019-12-032-11/+13
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| * | attempt to fix formattingPepijn de Vos2019-11-252-292/+292
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| * | gowin: add and test dff init valuesPepijn de Vos2019-11-254-41/+495
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* | | Merge pull request #1542 from YosysHQ/dave/abc9-loop-fixDavid Shah2019-12-022-29/+46
|\ \ \ | | | | | | | | abc9: Fix breaking of SCCs
| * | | abc9: Fix breaking of SCCsDavid Shah2019-12-012-29/+46
| | |/ | |/| | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | Merge pull request #1539 from YosysHQ/mwk/ilang-bounds-checkClifford Wolf2019-12-011-0/+4
|\ \ \ | |/ / |/| | read_ilang: do bounds checking on bit indices
| * | read_ilang: do bounds checking on bit indicesMarcin Kościelnicki2019-11-271-0/+4
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* | | Merge pull request #1540 from YosysHQ/mwk/xilinx-bufpllMiodrag Milanović2019-11-292-0/+21
|\ \ \ | | | | | | | | xilinx: Add missing blackbox cell for BUFPLL.
| * | | xilinx: Add missing blackbox cell for BUFPLL.Marcin Kościelnicki2019-11-292-0/+21
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* | | | Revert "Fold loop"Eddie Hung2019-11-271-3/+6
| |/ / |/| | | | | | | | This reverts commit a30d5e1cc35791a98b2269c5e587c566fe8b0a35.
* | | Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladdEddie Hung2019-11-272-3/+72
|\ \ \ | | | | | | | | xilinx_dsp: consider sign and zero-extension when packing post-multiplier adder
| * | | No need for -abc9Eddie Hung2019-11-261-1/+1
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| * | | Add citationEddie Hung2019-11-261-0/+1
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| * | | Check for either sign or zero extension for postAdd packingEddie Hung2019-11-261-3/+3
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| * | | Add testcase derived from fastfir_dynamictaps benchmarkEddie Hung2019-11-261-0/+68
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* | | Merge pull request #1501 from YosysHQ/dave/mem_copy_attrClifford Wolf2019-11-271-0/+4
|\ \ \ | | | | | | | | memory_collect: Copy attr from RTLIL::Memory to cell
| * | | memory_collect: Copy attr from RTLIL::Memory to cellDavid Shah2019-11-181-0/+4
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | Merge pull request #1534 from YosysHQ/mwk/opt_share-fixClifford Wolf2019-11-272-4/+24
|\ \ \ \ | | | | | | | | | | opt_share: Fix handling of fine cells.
| * | | | opt_share: Fix handling of fine cells.Marcin Kościelnicki2019-11-272-4/+24
| | |/ / | |/| | | | | | | | | | Fixes #1525.
* | | | Merge pull request #1535 from YosysHQ/eddie/write_xaiger_improveEddie Hung2019-11-272-22/+5
|\ \ \ \ | |/ / / |/| | | write_xaiger improvements
| * | | latch -> boxEddie Hung2019-11-261-1/+1
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| * | | Remove notesEddie Hung2019-11-261-9/+0
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| * | | Fold loopEddie Hung2019-11-261-6/+3
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| * | | Do not sigmap keep bits inside write_xaigerEddie Hung2019-11-261-1/+1
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| * | | xaiger: do not promote output wiresEddie Hung2019-11-261-5/+0
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* | | xilinx: Add simulation models for IOBUF and OBUFT.Marcin Kościelnicki2019-11-263-25/+30
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* | | clkbufmap: Add support for inverters in clock path.Marcin Kościelnicki2019-11-254-6/+69
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* | | xilinx: Use INV instead of LUT1 when applicableMarcin Kościelnicki2019-11-255-10/+14
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* | Merge pull request #1520 from pietrmar/fix-1463Eddie Hung2019-11-221-2/+0
|\ \ | | | | | | coolrunner2: remove spurious log_pop() call, fixes #1463
| * | coolrunner2: remove spurious log_pop() call, fixes #1463Martin Pietryka2019-11-231-2/+0
|/ / | | | | | | | | | | | | This was causing a segmentation fault because there is no accompanying log_push() call so header_count.size() became -1. Signed-off-by: Martin Pietryka <martin@pietryka.at>
* | Merge pull request #1517 from YosysHQ/clifford/optmemClifford Wolf2019-11-223-0/+146
|\ \ | | | | | | Add "opt_mem" pass
| * | Add "opt_mem" passClifford Wolf2019-11-223-0/+146
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Merge pull request #1515 from YosysHQ/clifford/svastuffClifford Wolf2019-11-222-7/+39
|\ \ \ | |/ / |/| | Add Verific/SVA support for "always" and "nexttime" properties
| * | Add Verific support for SVA nexttime propertiesClifford Wolf2019-11-221-0/+22
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Improve handling of verific primitives in "verific -import -V" modeClifford Wolf2019-11-221-2/+2
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add Verific SVA support for "always" propertiesClifford Wolf2019-11-221-5/+15
|/ / | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #1511 from YosysHQ/dave/alwaysClifford Wolf2019-11-226-9/+126
|\ \ | | | | | | sv: Error checking for always_comb, always_latch and always_ff
| * | Update CHANGELOG and READMEDavid Shah2019-11-222-0/+7
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | sv: Add tests for SV always typesDavid Shah2019-11-211-0/+63
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
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