| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | | * | | | | | | | | | | | | | | | | | | | | | | | | | fix mixing signals on FF mapping | Miodrag Milanovic | 2019-08-11 | 1 | -4/+4 | |
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| | | * | | | | | | | | | | | | | | | | | | | | | | | | | Replaced custom step with setundef | Miodrag Milanovic | 2019-08-11 | 3 | -91/+1 | |
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| | | * | | | | | | | | | | | | | | | | | | | | | | | | | Fixed data width | Miodrag Milanovic | 2019-08-11 | 1 | -2/+2 | |
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| | | * | | | | | | | | | | | | | | | | | | | | | | | | | Adding new pass to fix carry chain | Miodrag Milanovic | 2019-08-11 | 3 | -0/+124 | |
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| | | * | | | | | | | | | | | | | | | | | | | | | | | | | cleanup | Miodrag Milanovic | 2019-08-11 | 1 | -4/+7 | |
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| | | * | | | | | | | | | | | | | | | | | | | | | | | | | Fix CO | Miodrag Milanovic | 2019-08-09 | 1 | -26/+24 | |
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| | | * | | | | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'upstream/master' into efinix | Miodrag Milanovic | 2019-08-09 | 58 | -598/+1321 | |
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| | | * | | | | | | | | | | | | | | | | | | | | | | | | | | clock for ram trough gbuf | Miodrag Milanovic | 2019-08-04 | 1 | -0/+6 | |
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| | | * | | | | | | | | | | | | | | | | | | | | | | | | | | Added bram support | Miodrag Milanovic | 2019-08-04 | 6 | -1/+260 | |
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| | | * | | | | | | | | | | | | | | | | | | | | | | | | | | Custom step to add global clock buffers | Miodrag Milanovic | 2019-08-03 | 4 | -1/+129 | |
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| | | * | | | | | | | | | | | | | | | | | | | | | | | | | | Initial EFINIX support | Miodrag Milanovic | 2019-08-03 | 5 | -0/+370 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1316 from YosysHQ/eddie/fix_mem2reg | Clifford Wolf | 2019-08-22 | 2 | -0/+17 | |
| | |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | |_|_|_|_|_|_|_|/ / / / / / / / / / / / / / / / / / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | mem2reg to preserve user attributes and src | |||||
| | | * | | | | | | | | | | | | | | | | | | | | | | | | | | mem2reg to preserve user attributes and src | Eddie Hung | 2019-08-21 | 2 | -0/+17 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1315 from mmicko/fix_dependencies | whitequark | 2019-08-21 | 1 | -1/+1 | |
| | |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | |/ / / / / / / / / / / / / / / / / / / / / / / / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | Fix test_pmgen deps | |||||
| | | * | | | | | | | | | | | | | | | | | | | | | | | | | Fix test_pmgen deps | Miodrag Milanovic | 2019-08-21 | 1 | -1/+1 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1314 from YosysHQ/eddie/fix_techmap | Clifford Wolf | 2019-08-21 | 4 | -4/+21 | |
| | |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | |_|_|_|_|_|_|_|_|/ / / / / / / / / / / / / / / | | |/| | | | | | | | | / / / / / / / / / / / / / / | | |_|_|_|_|_|_|_|_|_|/ / / / / / / / / / / / / / | |/| | | | | | | | | | | | | | | | | | | | | | | | techmap -max_iter to apply to each module individually | |||||
| | | * | | | | | | | | | | | | | | | | | | | | | | | Grammar | Eddie Hung | 2019-08-20 | 1 | -1/+1 | |
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| | | * | | | | | | | | | | | | | | | | | | | | | | | Add test | Eddie Hung | 2019-08-20 | 3 | -0/+15 | |
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| | | * | | | | | | | | | | | | | | | | | | | | | | | techmap -max_iter to apply to each module individually | Eddie Hung | 2019-08-20 | 1 | -4/+6 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | Missing newline | Eddie Hung | 2019-08-20 | 1 | -1/+1 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | Fix copy-paste typo | Eddie Hung | 2019-08-20 | 1 | -1/+1 | |
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| * | | | | | | | | | / / / / / / / / / / / / / | Revert "Remove sequential extension" | Eddie Hung | 2019-08-20 | 9 | -68/+730 | |
| | |_|_|_|_|_|_|_|_|/ / / / / / / / / / / / / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 091bf4a18b2f4bf84fe62b61577c88d961468b3c. | |||||
| * | | | | | | | | | | | | | | | | | | | | | | Remove sequential extension | Eddie Hung | 2019-08-20 | 9 | -730/+68 | |
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| * | | | | | | | | | | | | | | | | | | | | | | Remove SRL* delays from cells_sim.v | Eddie Hung | 2019-08-20 | 1 | -5/+3 | |
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| * | | | | | | | | | | | | | | | | | | | | | | retime_mode -> dff_mode | Eddie Hung | 2019-08-20 | 1 | -7/+7 | |
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| * | | | | | | | | | | | | | | | | | | | | | | LUTMUX -> LUTMUX6 | Eddie Hung | 2019-08-20 | 1 | -2/+2 | |
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| * | | | | | | | | | | | | | | | | | | | | | | Cleanup techmap in map_luts | Eddie Hung | 2019-08-20 | 1 | -3/+5 | |
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| * | | | | | | | | | | | | | | | | | | | | | | Move `techmap abc_map.v` into map_luts | Eddie Hung | 2019-08-20 | 1 | -1/+2 | |
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| * | | | | | | | | | | | | | | | | | | | | | | Remove delays from abc_map.v | Eddie Hung | 2019-08-20 | 1 | -5/+2 | |
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| * | | | | | | | | | | | | | | | | | | | | | | Typo | Eddie Hung | 2019-08-20 | 1 | -1/+1 | |
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| * | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-08-20 | 5 | -16/+23 | |
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| | * | | | | | | | | | | | | | | | | | | | | | Merge pull request #1209 from YosysHQ/eddie/synth_xilinx | Eddie Hung | 2019-08-20 | 5 | -16/+23 | |
| | |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [WIP] synth xilinx renaming, as per #1184 | |||||
| | | * \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx | Eddie Hung | 2019-08-20 | 191 | -4502/+7003 | |
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| | | * | | | | | | | | | | | | | | | | | | | | | | Bump abc to fix &mfs bug | Eddie Hung | 2019-07-25 | 1 | -1/+1 | |
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| | | * | | | | | | | | | | | | | | | | | | | | | | Update changelog | Eddie Hung | 2019-07-22 | 1 | -3/+4 | |
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| | | * | | | | | | | | | | | | | | | | | | | | | | Update Makefile too | Eddie Hung | 2019-07-18 | 1 | -2/+2 | |
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| | | * | | | | | | | | | | | | | | | | | | | | | | Add CHANGELOG entry | Eddie Hung | 2019-07-18 | 1 | -0/+3 | |
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| | | * | | | | | | | | | | | | | | | | | | | | | | Work in progress for renaming labels/options in synth_xilinx | Eddie Hung | 2019-07-18 | 3 | -14/+17 | |
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| * | | | | | | | | | | | | | | | | | | | | | | | Do not sigmap! | Eddie Hung | 2019-08-20 | 1 | -2/+2 | |
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| * | | | | | | | | | | | | | | | | | | | | | | | Deprecate `abc_scc_break` attribute | Eddie Hung | 2019-08-20 | 1 | -8/+0 | |
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| * | | | | | | | | | | | | | | | | | | | | | | | Wrap SRL{16,32} too | Eddie Hung | 2019-08-20 | 3 | -7/+98 | |
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| * | | | | | | | | | | | | | | | | | | | | | | | Wrap LUTRAMs in order to capture comb/seq behaviour | Eddie Hung | 2019-08-20 | 5 | -36/+200 | |
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| * | | | | | | | | | | | | | | | | | | | | | | | Minor refactor | Eddie Hung | 2019-08-20 | 1 | -7/+6 | |
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| * | | | | | | | | | | | | | | | | | | | | | | | Add LUTRAM delays | Eddie Hung | 2019-08-20 | 1 | -3/+6 | |
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| * | | | | | | | | | | | | | | | | | | | | | | | Fix use of {CLK,EN}_POLARITY, also add a FIXME | Eddie Hung | 2019-08-20 | 1 | -65/+13 | |
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| * | | | | | | | | | | | | | | | | | | | | | | | Remove mapping rules | Eddie Hung | 2019-08-20 | 1 | -33/+0 | |
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| * | | | | | | | | | | | | | | | | | | | | | | | Remove -icells | Eddie Hung | 2019-08-20 | 1 | -2/+2 | |
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| * | | | | | | | | | | | | | | | | | | | | | | | Use abc_{map,unmap,model}.v | Eddie Hung | 2019-08-20 | 8 | -141/+334 | |
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| * | | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-08-20 | 24 | -112/+857 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1304 from YosysHQ/eddie/abc9_refactor | Eddie Hung | 2019-08-20 | 6 | -104/+138 | |
| | |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor abc9 to use port attributes, not module attributes | |||||
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index : iCE40/yosys | |
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